Speed up register read.
Don't scan an extra sequence just to read the return value.
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parent
27b94d36d0
commit
1fdcfa7082
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@ -406,6 +406,7 @@ static void cache_set(struct target *target, unsigned int index, uint32_t data)
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info->dram_cache[index].data == data) {
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info->dram_cache[index].data == data) {
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// This is already preset on the target.
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// This is already preset on the target.
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LOG_DEBUG("Cache hit at 0x%x for data 0x%x", index, data);
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LOG_DEBUG("Cache hit at 0x%x for data 0x%x", index, data);
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assert(dram_read32(target, index) == info->dram_cache[index].data);
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return;
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return;
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}
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}
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info->dram_cache[index].data = data;
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info->dram_cache[index].data = data;
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@ -427,6 +428,30 @@ static void dump_debug_ram(struct target *target)
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}
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}
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}
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}
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/* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
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static void cache_invalidate(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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info->dram_cache[i].valid = false;
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info->dram_cache[i].dirty = false;
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}
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}
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/* Called by cache_write() after the program has run. Also call this if you're
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* running programs without calling cache_write(). */
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static void cache_clean(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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if (i >= 4) {
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info->dram_cache[i].valid = false;
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} else {
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info->dram_cache[i].dirty = false;
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}
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}
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}
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/** Write cache to the target, and optionally run the program. */
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/** Write cache to the target, and optionally run the program. */
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static int cache_write(struct target *target, unsigned int address, bool run)
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static int cache_write(struct target *target, unsigned int address, bool run)
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{
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{
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@ -553,6 +578,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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}
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}
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info->dram_cache[i].dirty = false;
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info->dram_cache[i].dirty = false;
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}
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}
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cache_clean(target);
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if (wait_for_debugint_clear(target, true) != ERROR_OK) {
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if (wait_for_debugint_clear(target, true) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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LOG_ERROR("Debug interrupt didn't clear.");
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@ -561,6 +587,8 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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}
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}
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} else {
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} else {
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cache_clean(target);
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int interrupt = buf_get_u32(in + 8*(scan-1), DBUS_DATA_START + 33, 1);
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int interrupt = buf_get_u32(in + 8*(scan-1), DBUS_DATA_START + 33, 1);
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if (interrupt) {
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if (interrupt) {
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info->interrupt_high_count++;
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info->interrupt_high_count++;
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@ -570,14 +598,16 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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dump_debug_ram(target);
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dump_debug_ram(target);
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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}
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}
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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if (i >= 4) {
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info->dram_cache[i].valid = false;
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} else {
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} else {
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info->dram_cache[i].dirty = false;
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// We read a useful value in that last scan.
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unsigned int read_addr = buf_get_u32(in + 8*(scan-1), DBUS_ADDRESS_START, info->addrbits);
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if (read_addr != address) {
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LOG_INFO("Got data from 0x%x but expected it from 0x%x",
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read_addr, address);
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}
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info->dram_cache[read_addr].data =
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buf_get_u64(in + 8*(scan-1), DBUS_DATA_START, DBUS_DATA_SIZE);
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info->dram_cache[read_addr].valid = true;
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}
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}
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}
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}
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@ -586,14 +616,14 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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/* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
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uint32_t cache_get32(struct target *target, unsigned int address)
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static void cache_invalidate(struct target *target)
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{
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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if (!info->dram_cache[address].valid) {
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info->dram_cache[i].valid = false;
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info->dram_cache[address].data = dram_read32(target, address);
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info->dram_cache[i].dirty = false;
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info->dram_cache[address].valid = true;
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}
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}
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return info->dram_cache[address].data;
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}
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}
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#if 0
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#if 0
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@ -820,9 +850,9 @@ static int register_get(struct reg *reg)
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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uint32_t value = dram_read32(target, 4);
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uint32_t value = cache_get32(target, 4);
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uint32_t exception = dram_read32(target, info->dramsize-1);
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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if (exception) {
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LOG_ERROR("Got exception 0x%x when reading register %d", exception,
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LOG_ERROR("Got exception 0x%x when reading register %d", exception,
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reg->number);
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reg->number);
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@ -1570,6 +1600,8 @@ static int riscv_write_memory(struct target *target, uint32_t address,
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// batch.
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// batch.
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LOG_INFO("Retrying memory write starting from 0x%x with more delays", address + size * i);
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LOG_INFO("Retrying memory write starting from 0x%x with more delays", address + size * i);
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cache_clean(target);
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if (write_gpr(target, T0, address + size * i) != ERROR_OK) {
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if (write_gpr(target, T0, address + size * i) != ERROR_OK) {
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goto error;
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goto error;
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}
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}
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@ -1586,6 +1618,7 @@ static int riscv_write_memory(struct target *target, uint32_t address,
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free(out);
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free(out);
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free(field);
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free(field);
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cache_clean(target);
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return register_write(target, T0, t0);
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return register_write(target, T0, t0);
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error:
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error:
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