From 42441fd96cf86ffca61f77afe24aae21fb00bb89 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Thu, 19 Oct 2023 19:07:29 -0700 Subject: [PATCH 01/18] target: Add a debug_reason command This allows programmatically determining the debug reason. Change-Id: I0c3e85cebb6dc28fc0fc212beca84a484ac654a5 Signed-off-by: Peter Collingbourne Reviewed-on: https://review.openocd.org/c/openocd/+/7952 Reviewed-by: Jan Matyas Reviewed-by: Tomas Vanek Reviewed-by: Antonio Borneo Tested-by: jenkins --- doc/openocd.texi | 12 ++++++++++++ src/target/target.c | 19 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/doc/openocd.texi b/doc/openocd.texi index a2965189f..45c2e4df5 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5296,6 +5296,18 @@ Displays the current target state: (Also, @pxref{eventpolling,,Event Polling}.) @end deffn +@deffn {Command} {$target_name debug_reason} +Displays the current debug reason: +@code{debug-request}, +@code{breakpoint}, +@code{watchpoint}, +@code{watchpoint-and-breakpoint}, +@code{single-step}, +@code{target-not-halted}, +@code{program-exit}, +@code{exception-catch} or @code{undefined}. +@end deffn + @deffn {Command} {$target_name eventlist} Displays a table listing all event handlers currently associated with this target. diff --git a/src/target/target.c b/src/target/target.c index 61c243510..d368cb515 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -5874,6 +5874,18 @@ COMMAND_HANDLER(handle_target_current_state) return ERROR_OK; } +COMMAND_HANDLER(handle_target_debug_reason) +{ + if (CMD_ARGC != 0) + return ERROR_COMMAND_SYNTAX_ERROR; + + struct target *target = get_current_target(CMD_CTX); + + command_print(CMD, "%s", debug_reason_name(target)); + + return ERROR_OK; +} + static int jim_target_invoke_event(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { struct jim_getopt_info goi; @@ -6025,6 +6037,13 @@ static const struct command_registration target_instance_command_handlers[] = { .help = "displays the current state of this target", .usage = "", }, + { + .name = "debug_reason", + .mode = COMMAND_EXEC, + .handler = handle_target_debug_reason, + .help = "displays the debug reason of this target", + .usage = "", + }, { .name = "arp_examine", .mode = COMMAND_EXEC, From 00b07390826f7cd5f72bc036e3907a87c6cbc33d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 13:51:51 -0500 Subject: [PATCH 02/18] tcl/target/ti_k3: Convert sysctrl ap port num as a variable Convert the sysctrl ap port num as a variable to allow support for the AM2x family of K3 SoCs. Change-Id: I1b5b55e48240e6654779dd636fdf07bca055e192 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7941 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/target/ti_k3.cfg | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 1cd85eec3..78ee8b2ca 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -44,6 +44,7 @@ set CM3_CTIBASE {0x3C016000} # sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x44} +set _sysctrl_ap_num 7 # All the ARMV8s are the next processors. # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1 @@ -266,9 +267,11 @@ set _TARGETNAME $_CHIPNAME.cpu set _CTINAME $_CHIPNAME.cti # sysctrl is always present -cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0] +cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \ + -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0] -target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \ +target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \ + -ap-num $_sysctrl_ap_num -defer-examine \ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl] $_TARGETNAME.sysctrl configure -event reset-assert { } From 4b879bb01737f11a11f05c3b4feb09e6ddc85a5d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 13:56:00 -0500 Subject: [PATCH 03/18] tcl/target/ti_k3: Convert Cortex-R5 ap port num as a variable Convert the Cortex-R5 ap port num as a variable to allow support for the AM2x family of K3 SoCs. Change-Id: I7dc8b459dca8b5f21395230b5cb782b14538bd48 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7942 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/target/ti_k3.cfg | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 78ee8b2ca..e05b81a17 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -56,6 +56,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000} set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000} set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000} set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} +set _r5_ap_num 1 # Finally an General Purpose(GP) MCU set CM4_CTIBASE {0x20001000} @@ -359,12 +360,12 @@ if { $_v8_smp_debug == 0 } { for { set _core 0 } { $_core < $_r5_cores } { incr _core } { set _r5_name [lindex $R5_NAMES $_core] - cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \ + cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \ -baseaddr [lindex $R5_CTIBASE $_core] # inactive core examination will fail - wait till startup of additional core target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \ + -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name] $_TARGETNAME.$_r5_name configure -event gdb-attach { From 5ea20d7ed99e252947a85f93db870109cc094efc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Oct 2023 13:45:39 -0500 Subject: [PATCH 04/18] tcl/target/ti_k3: Convert memory access ap port num as a variable Convert the memory access ap port num as a variable to allow support for the AM2x family of K3 SoCs. Change-Id: Ibd96c94055721f60d95179dab21d014c15b0f562 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7943 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/target/ti_k3.cfg | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index e05b81a17..bb2a991ce 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -66,6 +66,9 @@ set _gp_mcu_cores 0 # General Purpose MCU power-ap unlock offsets set _gp_mcu_ap_unlock_offsets {0xf0 0x60} +# Generic mem-ap port number +set _mem_ap_num 2 + # Set configuration overrides for each SOC switch $_soc { am654 { @@ -423,5 +426,5 @@ if { 0 == [string compare [adapter name] dmem ] } { } } else { # AXI AP access port for SoC address map - target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2 + target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num } From 9a79dfb709ad84d243cb866928b4253c7ea45078 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 15:36:55 -0500 Subject: [PATCH 05/18] tcl/target/ti_k3: Make Cortex-A processors optional The AM2x family of K3 SoCs typically do not contain a Cortex-A53 or A72 processor. So, make the cpu "up" functions available when armv8 processor count > 0. Change-Id: I985b194fe7cc63e4134ad84ccd921cc456eb412f Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7944 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/target/ti_k3.cfg | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index bb2a991ce..4e563f2be 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -341,24 +341,26 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { } } -# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs -set _armv8_up_cmd "$_armv8_cpu_name"_up -# Available if V8_SMP_DEBUG is set to non-zero value -set _armv8_smp_cmd "$_armv8_cpu_name"_smp +if { $_armv8_cores > 0 } { + # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs + set _armv8_up_cmd "$_armv8_cpu_name"_up + # Available if V8_SMP_DEBUG is set to non-zero value + set _armv8_smp_cmd "$_armv8_cpu_name"_smp -if { $_v8_smp_debug == 0 } { - proc $_armv8_up_cmd { args } { - foreach _core $args { - targets $_core - _cpu_no_smp_up + if { $_v8_smp_debug == 0 } { + proc $_armv8_up_cmd { args } { + foreach _core $args { + targets $_core + _cpu_no_smp_up + } } + } else { + proc $_armv8_smp_cmd { args } { + _armv8_smp_up + } + # Declare SMP + target smp {*}$_v8_smp_targets } -} else { - proc $_armv8_smp_cmd { args } { - _armv8_smp_up - } - # Declare SMP - target smp {*}$_v8_smp_targets } for { set _core 0 } { $_core < $_r5_cores } { incr _core } { From 7919b0965b1b75a9e1a8fe33defb83528196683e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 15:47:12 -0500 Subject: [PATCH 06/18] tcl/target/ti_k3: Sort the SoC documentation alphabetically Sort the documentation for the TI K3 parts alphabetically. Change-Id: I2c40714ad590e3d9232a6f915c157d677e0c3610 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7945 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/target/ti_k3.cfg | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 4e563f2be..f1f8994f1 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -2,24 +2,24 @@ # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ # # Texas Instruments K3 devices: +# * AM625: https://www.ti.com/lit/pdf/spruiv7a +# Has 4 ARMV8 Cores and 1 R5 Core and an M4F +# * AM62A7: https://www.ti.com/lit/pdf/spruj16a +# Has 4 ARMV8 Cores and 2 R5 Cores +# * AM62P: https://www.ti.com/lit/pdf/spruj83 +# Has 4 ARMV8 Cores and 2 R5 Cores +# * AM642: https://www.ti.com/lit/pdf/spruim2 +# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 # * AM654x: https://www.ti.com/lit/pdf/spruid7 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3 -# * J721E: https://www.ti.com/lit/pdf/spruil1 -# Has 2 ARMV8 Cores and 6 R5 Cores and an M3 # * J7200: https://www.ti.com/lit/pdf/spruiu1 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3 +# * J721E: https://www.ti.com/lit/pdf/spruil1 +# Has 2 ARMV8 Cores and 6 R5 Cores and an M3 # * J721S2: https://www.ti.com/lit/pdf/spruj28 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52 # Has 8 ARMV8 Cores and 8 R5 Cores -# * AM642: https://www.ti.com/lit/pdf/spruim2 -# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 -# * AM625: https://www.ti.com/lit/pdf/spruiv7a -# Has 4 ARMV8 Cores and 1 R5 Core and an M4F -# * AM62a7: https://www.ti.com/lit/pdf/spruj16a -# Has 4 ARMV8 Cores and 2 R5 Cores -# * AM62P: https://www.ti.com/lit/pdf/spruj83 -# Has 4 ARMV8 Cores and 2 R5 Cores # source [find target/swj-dp.tcl] From a646057c7eaf52e077afac98405c2aa2fa7d96bb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 15:50:49 -0500 Subject: [PATCH 07/18] tcl/target/ti_k3: Add AM243 SoC Add support for the TI K3 family AM243 SoC. This SoC is built on the same base of AM642, so reuse the configuration with the exception of Cortex-A53 which is not available on this device. For further details, see https://www.ti.com/lit/pdf/spruim2 Change-Id: I971ba878b0f503e5120f6853634776eb61d05080 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7946 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/target/ti_k3.cfg | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index f1f8994f1..e4a235b29 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -2,6 +2,8 @@ # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ # # Texas Instruments K3 devices: +# * AM243: https://www.ti.com/lit/pdf/spruim2 +# Has 4 R5 Cores, M4F and an M3 # * AM625: https://www.ti.com/lit/pdf/spruiv7a # Has 4 ARMV8 Cores and 1 R5 Core and an M4F # * AM62A7: https://www.ti.com/lit/pdf/spruj16a @@ -85,6 +87,7 @@ switch $_soc { # Sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x50} } + am243 - am642 { set _K3_DAP_TAPID 0x0bb3802f @@ -102,6 +105,12 @@ switch $_soc { # M4 processor set _gp_mcu_cores 1 + + # Overrides for am243 + if { "$_soc" == "am243" } { + # Uses the same JTAG ID + set _armv8_cores 0 + } } am625 { set _K3_DAP_TAPID 0x0bb7e02f From ba39343e3d5e1c8878f314e496172d829c22e231 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 15:53:59 -0500 Subject: [PATCH 08/18] tcl/board: Add TI AM243 launchpad config Add basic connection details with AM243 Launchpad For further details, see: https://www.ti.com/tool/LP-AM243 Change-Id: Id8cec6675a222888b0007484209558d6503dbcda Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7947 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/board/ti_am243_launchpad.cfg | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tcl/board/ti_am243_launchpad.cfg diff --git a/tcl/board/ti_am243_launchpad.cfg b/tcl/board/ti_am243_launchpad.cfg new file mode 100644 index 000000000..aa75dda88 --- /dev/null +++ b/tcl/board/ti_am243_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM243 Launchpad +# https://www.ti.com/tool/LP-AM243 +# + +# AM243 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am243 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 From e4e94a355d4cfd79a98df8ceefa8432a3a14d076 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 16:00:27 -0500 Subject: [PATCH 09/18] tcl/target/ti_k3: Add AM263 SoC Add support for the TI K3 family AM263 SoC. For further details, see https://www.ti.com/lit/pdf/spruim2 Change-Id: I9a91b3d675511661dfc2710a7183bd59b98da133 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7948 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/target/ti_k3.cfg | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index e4a235b29..24b3fae87 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -4,6 +4,8 @@ # Texas Instruments K3 devices: # * AM243: https://www.ti.com/lit/pdf/spruim2 # Has 4 R5 Cores, M4F and an M3 +# * AM263: https://www.ti.com/lit/pdf/spruj17 +# Has 4 R5 Cores and an M3 # * AM625: https://www.ti.com/lit/pdf/spruiv7a # Has 4 ARMV8 Cores and 1 R5 Core and an M4F # * AM62A7: https://www.ti.com/lit/pdf/spruj16a @@ -73,6 +75,22 @@ set _mem_ap_num 2 # Set configuration overrides for each SOC switch $_soc { + am263 { + set _K3_DAP_TAPID 0x2bb7d02f + + # Mem-ap port + set _mem_ap_num 6 + + # AM263 has 0 ARMV8 CPUs + set _armv8_cores 0 + + # AM263 has 2 cluster of 2 R5s cores. + set _r5_cores 4 + set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} + set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000} + set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000} + set _r5_ap_num 5 + } am654 { set _K3_DAP_TAPID 0x0bb5a02f From 17f34355e550900c6563431c35517c8e082cd5e2 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 16:02:44 -0500 Subject: [PATCH 10/18] tcl/board: Add TI AM263 launchpad config Add basic connection details with AM263 Launchpad For further details, see: https://www.ti.com/tool/LP-AM263 Change-Id: I94c7a9ca70734ae89c6df3f02137d5bd32fde774 Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7949 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/board/ti_am263_launchpad.cfg | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tcl/board/ti_am263_launchpad.cfg diff --git a/tcl/board/ti_am263_launchpad.cfg b/tcl/board/ti_am263_launchpad.cfg new file mode 100644 index 000000000..a07a21b3d --- /dev/null +++ b/tcl/board/ti_am263_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM263 Launchpad +# https://www.ti.com/tool/LP-AM263 +# + +# AM263 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am263 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 From cb60f75a56ba54b5a52da00add5312f94bb67c86 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 16:07:41 -0500 Subject: [PATCH 11/18] tcl/target/ti_k3: Add AM273 SoC Add support for the TI K3 family AM273 SoC. For further details, see https://www.ti.com/lit/pdf/spruiu0 Change-Id: Ifa21d0760831f4f525ecd976fb8d086ffdbc9e9f Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7950 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/target/ti_k3.cfg | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index 24b3fae87..23825b86b 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -6,6 +6,8 @@ # Has 4 R5 Cores, M4F and an M3 # * AM263: https://www.ti.com/lit/pdf/spruj17 # Has 4 R5 Cores and an M3 +# * AM273: https://www.ti.com/lit/pdf/spruiu0 +# Has 2 R5 Cores and an M3 # * AM625: https://www.ti.com/lit/pdf/spruiv7a # Has 4 ARMV8 Cores and 1 R5 Core and an M4F # * AM62A7: https://www.ti.com/lit/pdf/spruj16a @@ -91,6 +93,25 @@ switch $_soc { set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000} set _r5_ap_num 5 } + am273 { + set _K3_DAP_TAPID 0x1bb6a02f + + # Mem-ap port + set _mem_ap_num 6 + + # system controller is on AP0 + set _sysctrl_ap_num 0 + + # AM273 has 0 ARMV8 CPUs + set _armv8_cores 0 + + # AM273 has 1 cluster of 2 R5s cores. + set _r5_cores 2 + set R5_NAMES {main0_r5.0 main0_r5.1} + set R5_DBGBASE {0x90030000 0x90032000} + set R5_CTIBASE {0x90038000 0x90039000} + set _r5_ap_num 5 + } am654 { set _K3_DAP_TAPID 0x0bb5a02f From 5b878b6e8b23d4c4b7aa3bf157c262e4f8620882 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 17 Oct 2023 16:10:17 -0500 Subject: [PATCH 12/18] tcl/board: Add TI AM273 launchpad config Add basic connection details with AM273 Launchpad For further details, see: https://www.ti.com/tool/LP-AM273 Change-Id: I88a02cdbccb65c185e808503d080cc1f12c909ae Signed-off-by: Nishanth Menon Reviewed-on: https://review.openocd.org/c/openocd/+/7951 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/board/ti_am273_launchpad.cfg | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tcl/board/ti_am273_launchpad.cfg diff --git a/tcl/board/ti_am273_launchpad.cfg b/tcl/board/ti_am273_launchpad.cfg new file mode 100644 index 000000000..c17170bf1 --- /dev/null +++ b/tcl/board/ti_am273_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM273 Launchpad +# https://www.ti.com/tool/LP-AM273 +# + +# AM273 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am273 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 From d378c3a1d637b61afd4c4f9c2c075cc05be2cb9d Mon Sep 17 00:00:00 2001 From: Daniel Anselmi Date: Mon, 25 Sep 2023 00:05:38 +0200 Subject: [PATCH 13/18] pld/certus: fix crash when loading bitstream Loading a bitstream to cetrus device crashed due to missing initialization. Change-Id: Ibd9a04b84e514f9635af01a2b73bae478e534eb7 Signed-off-by: Daniel Anselmi Reviewed-on: https://review.openocd.org/c/openocd/+/7908 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/pld/certus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/pld/certus.c b/src/pld/certus.c index a49501f54..ccb3feb90 100644 --- a/src/pld/certus.c +++ b/src/pld/certus.c @@ -121,6 +121,7 @@ static int lattice_certus_enable_programming(struct jtag_tap *tap) uint8_t buffer = 0; field.num_bits = 8; field.out_value = &buffer; + field.in_value = NULL; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); jtag_add_runtest(2, TAP_IDLE); return jtag_execute_queue(); From edf8e916a266b5df15f456fcec748caf6b2b350c Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 9 Nov 2023 15:12:08 +0100 Subject: [PATCH 14/18] LICENSES: Add the CC0-1.0 license Add the full text of the CC0-1.0 license to the OpenOCD tree. It was copied directly from: https://spdx.org/licenses/CC0-1.0.html#licenseText Add the required tags for reference and tooling. Change-Id: Iae9c1431b6ffdd68ad5780deb78a257edb0b67f3 Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/7994 Tested-by: jenkins Reviewed-by: Karl Palsson --- LICENSES/preferred/CC0-1.0 | 130 +++++++++++++++++++++++++++++++++++++ Makefile.am | 1 + 2 files changed, 131 insertions(+) create mode 100644 LICENSES/preferred/CC0-1.0 diff --git a/LICENSES/preferred/CC0-1.0 b/LICENSES/preferred/CC0-1.0 new file mode 100644 index 000000000..ba3c8c795 --- /dev/null +++ b/LICENSES/preferred/CC0-1.0 @@ -0,0 +1,130 @@ +Valid-License-Identifier: CC0-1.0 +SPDX-URL: https://spdx.org/licenses/CC0-1.0.html +Usage-Guide: + To use the Creative Commons Zero v1.0 Universal License put the following + SPDX tag/value pair into a comment according to the placement guidelines in + the licensing rules documentation: + SPDX-License-Identifier: CC0-1.0 +License-Text: + +Creative Commons Legal Code + +CC0 1.0 Universal + + CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE + LEGAL SERVICES. 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Should any part of the License for any +reason be judged legally invalid or ineffective under applicable law, such +partial invalidity or ineffectiveness shall not invalidate the remainder +of the License, and in such case Affirmer hereby affirms that he or she +will not (i) exercise any of his or her remaining Copyright and Related +Rights in the Work or (ii) assert any associated claims and causes of +action with respect to the Work, in either case contrary to Affirmer's +express Statement of Purpose. + +4. Limitations and Disclaimers. + + a. No trademark or patent rights held by Affirmer are waived, abandoned, + surrendered, licensed or otherwise affected by this document. + b. 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Affirmer understands and acknowledges that Creative Commons is not a + party to this document and has no duty or obligation with respect to + this CC0 or use of the Work. diff --git a/Makefile.am b/Makefile.am index a4f77adc2..153c471a9 100644 --- a/Makefile.am +++ b/Makefile.am @@ -64,6 +64,7 @@ EXTRA_DIST += \ LICENSES/preferred/BSD-2-Clause-Views \ LICENSES/preferred/BSD-3-Clause \ LICENSES/preferred/BSD-Source-Code \ + LICENSES/preferred/CC0-1.0 \ LICENSES/preferred/GFDL-1.2 \ LICENSES/preferred/gfdl-1.2.texi.readme \ LICENSES/preferred/GPL-2.0 \ From 9fcf33da8e09fb93a1f3f1eb0409e64a820698b4 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 9 Nov 2023 15:15:10 +0100 Subject: [PATCH 15/18] contrib/rtos-helpers/FreeRTOS-openocd: change license to CC0-1.0 This file is intended to be included in any user's project that plans to use OpenOCD awareness for FreeRTOS. It is supposed to be distributed under a permissive license to not impact the original license of the user's project. Distribute it under Creative Commons Zero v1.0 Universal license. Change-Id: I7ac90e8b742517bcafc08c00662625671c8159c4 Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/7995 Reviewed-by: Karl Palsson Reviewed-by: Paul Fertser Tested-by: jenkins --- contrib/rtos-helpers/FreeRTOS-openocd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/rtos-helpers/FreeRTOS-openocd.c b/contrib/rtos-helpers/FreeRTOS-openocd.c index 000453d5d..5f82ac7a2 100644 --- a/contrib/rtos-helpers/FreeRTOS-openocd.c +++ b/contrib/rtos-helpers/FreeRTOS-openocd.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-License-Identifier: CC0-1.0 /* * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer From 5587710c1a0537df78d87bcc0472e25a974d91c1 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 4 Nov 2023 15:55:24 +0100 Subject: [PATCH 16/18] nor: rsl10: fix minor coding style I use a script to compare the commands in the code with the ones in the documentation. Fix the style of the data to simplify the parsing. Change-Id: I0f1d7e9ff5e2928312ca1a2f3424f82d2910580a Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/7960 Tested-by: jenkins Reviewed-by: zapb --- src/flash/nor/rsl10.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/flash/nor/rsl10.c b/src/flash/nor/rsl10.c index 5f0ac9b8f..c286e9ac8 100644 --- a/src/flash/nor/rsl10.c +++ b/src/flash/nor/rsl10.c @@ -815,7 +815,8 @@ static const struct command_registration rsl10_exec_command_handlers[] = { .help = "Mass erase all unprotected flash areas", .usage = "", }, - COMMAND_REGISTRATION_DONE}; + COMMAND_REGISTRATION_DONE +}; static const struct command_registration rsl10_command_handlers[] = { { @@ -825,7 +826,8 @@ static const struct command_registration rsl10_command_handlers[] = { .usage = "", .chain = rsl10_exec_command_handlers, }, - COMMAND_REGISTRATION_DONE}; + COMMAND_REGISTRATION_DONE +}; const struct flash_driver rsl10_flash = { .name = "rsl10", From b39072f2ef72f02601b40931d3a38c465804a906 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 5 Nov 2023 12:55:27 +0100 Subject: [PATCH 17/18] target: use boolean values for 'valid' and 'dirty' flags Convert to boolean the remaining numeric assignment and comparison Change-Id: Idc25221d93e85236185aab9ee36f0a379939c89c Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/7961 Reviewed-by: zapb Tested-by: jenkins --- src/target/arc.c | 10 +++++----- src/target/etm.c | 4 ++-- src/target/mips64.c | 16 ++++++++-------- src/target/mips_mips64.c | 8 ++++---- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/target/arc.c b/src/target/arc.c index 45005b29b..0f7b11025 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -1265,8 +1265,8 @@ static int arc_resume(struct target *target, int current, target_addr_t address, /* current = 1: continue on current PC, otherwise continue at
*/ if (!current) { target_buffer_set_u32(target, pc->value, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address); } @@ -1281,7 +1281,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address, resume_pc, pc->dirty, pc->valid); /* check if GDB tells to set our PC where to continue from */ - if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) { + if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) { value = target_buffer_get_u32(target, pc->value); LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value); CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value)); @@ -2007,8 +2007,8 @@ static int arc_step(struct target *target, int current, target_addr_t address, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) { buf_set_u32(pc->value, 0, 32, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; } LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32, diff --git a/src/target/etm.c b/src/target/etm.c index 6718875ee..d083017f7 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -552,8 +552,8 @@ static int etm_set_reg(struct reg *reg, uint32_t value) } buf_set_u32(reg->value, 0, reg->size, value); - reg->valid = 1; - reg->dirty = 0; + reg->valid = true; + reg->dirty = false; return ERROR_OK; } diff --git a/src/target/mips64.c b/src/target/mips64.c index 37f36855c..48f4563dc 100644 --- a/src/target/mips64.c +++ b/src/target/mips64.c @@ -247,8 +247,8 @@ static int mips64_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_set_u64(reg->value, 0, 64, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -265,8 +265,8 @@ static int mips64_read_core_reg(struct target *target, int num) reg_value = mips64->core_regs[num]; buf_set_u64(mips64->core_cache->reg_list[num].value, 0, 64, reg_value); - mips64->core_cache->reg_list[num].valid = 1; - mips64->core_cache->reg_list[num].dirty = 0; + mips64->core_cache->reg_list[num].valid = true; + mips64->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -284,8 +284,8 @@ static int mips64_write_core_reg(struct target *target, int num) reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64); mips64->core_regs[num] = reg_value; LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value); - mips64->core_cache->reg_list[num].valid = 1; - mips64->core_cache->reg_list[num].dirty = 0; + mips64->core_cache->reg_list[num].valid = true; + mips64->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -297,8 +297,8 @@ int mips64_invalidate_core_regs(struct target *target) unsigned int i; for (i = 0; i < mips64->core_cache->num_regs; i++) { - mips64->core_cache->reg_list[i].valid = 0; - mips64->core_cache->reg_list[i].dirty = 0; + mips64->core_cache->reg_list[i].valid = false; + mips64->core_cache->reg_list[i].dirty = false; } return ERROR_OK; diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c index bf6095358..9921e9380 100644 --- a/src/target/mips_mips64.c +++ b/src/target/mips_mips64.c @@ -625,8 +625,8 @@ static int mips_mips64_resume(struct target *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) { buf_set_u64(pc->value, 0, 64, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; } resume_pc = buf_get_u64(pc->value, 0, 64); @@ -717,8 +717,8 @@ static int mips_mips64_step(struct target *target, int current, *
*/ if (!current) { buf_set_u64(pc->value, 0, 64, address); - pc->dirty = 1; - pc->valid = 1; + pc->dirty = true; + pc->valid = true; } /* the front-end may request us not to handle breakpoints */ From d4575b647a3603200a9bb4a784d170f792ab88d0 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 5 Nov 2023 17:02:26 +0100 Subject: [PATCH 18/18] target: fix segmentation fault on target create In the unusual (and even incorrect) case of running the command target create ... before defining an adapter and the associated transport, the command causes a segmentation fault. E.g.: openocd -c 'target create cpu cortex-m -endian little' Check that get_current_transport() returns a valid pointer before referencing it. Change-Id: I9796a7e92196ef3df5c7152b27c34102045dc9e7 Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/7962 Reviewed-by: Tomas Vanek Tested-by: jenkins --- src/target/target.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/target.c b/src/target/target.c index d368cb515..148bc9fb7 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -6143,7 +6143,7 @@ static int target_create(struct jim_getopt_info *goi) if (e != JIM_OK) return e; struct transport *tr = get_current_transport(); - if (tr->override_target) { + if (tr && tr->override_target) { e = tr->override_target(&cp); if (e != ERROR_OK) { LOG_ERROR("The selected transport doesn't support this target");