interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

LPC1788 target configuration file. 

Change-Id: I68bd6b7c19d9d1bee13d0921c32b4490e68ab8f2
Signed-off-by: is2t <devel@is2t.com>
Reviewed-on: http://openocd.zylin.com/1002
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
is2t 2012-12-07 08:15:03 +01:00 committed by Spencer Oliver
parent 71d43007c6
commit 1e07f7bb6a
1 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
tcl/target/lpc1788.cfg Normal file
View File

@ -0,0 +1,20 @@
# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
set CHIPNAME lpc1788
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x10000
set CPUROMSIZE 0x80000
# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000
#Include the main configuration file.
source [find target/lpc17xx.cfg];
# if srst is not fitted, use SYSRESETREQ to perform a soft reset
cortex_m3 reset_config sysresetreq