ARM11: remove arm11->target
Don't need/want arm11->target; we have arm11->arm.target instead. Also remove some unused watchpoint stuff.
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c2af99d471
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1d29440a9c
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@ -127,13 +127,14 @@ static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
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* the target.
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*/
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arm11->target->state = TARGET_HALTED;
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arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
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arm11->arm.target->state = TARGET_HALTED;
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arm11->arm.target->debug_reason =
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arm11_get_DSCR_debug_reason(*dscr);
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}
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else
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{
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arm11->target->state = TARGET_RUNNING;
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arm11->target->debug_reason = DBG_REASON_NOTHALTED;
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arm11->arm.target->state = TARGET_RUNNING;
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arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
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}
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arm11_sc7_clear_vbw(arm11);
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@ -1221,8 +1222,6 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
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armv4_5_init_arch_info(target, &arm11->arm);
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arm11->target = target;
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arm11->jtag_info.tap = target->tap;
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arm11->jtag_info.scann_size = 5;
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arm11->jtag_info.scann_instr = ARM11_SCAN_N;
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@ -1313,7 +1312,6 @@ static int arm11_examine(struct target *target)
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/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
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arm11->free_brps = arm11->brp;
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arm11->free_wrps = arm11->wrp;
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LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
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device_id, implementor, didr);
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@ -1350,7 +1348,8 @@ static int arm11_examine(struct target *target)
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/** Load a register that is marked !valid in the register cache */
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static int arm11_get_reg(struct reg *reg)
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{
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struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
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struct arm11_reg_state *r = reg->arch_info;
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struct target *target = r->target;
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if (target->state != TARGET_HALTED)
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{
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@ -1371,7 +1370,8 @@ static int arm11_get_reg(struct reg *reg)
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/** Change a value in the register cache */
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static int arm11_set_reg(struct reg *reg, uint8_t *buf)
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{
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struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
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struct arm11_reg_state *r = reg->arch_info;
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struct target *target = r->target;
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struct arm11_common *arm11 = target_to_arm11(target);
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// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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@ -51,18 +51,13 @@ enum arm11_debug_version
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struct arm11_common
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{
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struct arm arm;
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struct target * target; /**< Reference back to the owner */
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/** Debug module state. */
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struct arm_dpm dpm;
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/** \name Processor type detection */
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/*@{*/
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size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
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size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
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/*@}*/
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size_t free_brps; /**< Number of breakpoints allocated */
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uint32_t last_dscr; /**< Last retrieved DSCR value;
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Use only for debug message generation */
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@ -77,8 +72,6 @@ struct arm11_common
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/*@}*/
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size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
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size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
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// GA
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struct reg_cache *core_cache;
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@ -85,7 +85,7 @@ int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t
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*/
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void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
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{
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field->tap = arm11->target->tap;
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field->tap = arm11->arm.target->tap;
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field->num_bits = num_bits;
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field->out_value = out_data;
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field->in_value = in_data;
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@ -102,8 +102,7 @@ void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_dat
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*/
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void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
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{
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struct jtag_tap *tap;
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tap = arm11->target->tap;
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struct jtag_tap *tap = arm11->arm.target->tap;
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if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
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{
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