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cortex_m: target implementation renames cortex_m3 to cortex_m 

We changed the actual target name quite a while ago.
This changes the actual target function names/defines to also match
this change.

Change-Id: I4f22fb107636db2279865b45350c9c776e608a75
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1626
Tested-by: jenkins
This commit is contained in:
Spencer Oliver 2013-10-10 21:16:42 +01:00
parent 43fc460559
commit 1c975fe30b
11 changed files with 373 additions and 376 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
contrib/loaders/README
View File

@ -7,7 +7,7 @@ checksum/armv4_5_crc.s :
- ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code - ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code
checksum/armv7m_crc.s : checksum/armv7m_crc.s :
- ARMv7m checksum loader : see target/armv7m.c:cortex_m3_crc_code - ARMv7m checksum loader : see target/armv7m.c:cortex_m_crc_code
checksum/mips32.s : checksum/mips32.s :
- MIPS32 checksum loader : see target/mips32.c:mips_crc_code - MIPS32 checksum loader : see target/mips32.c:mips_crc_code

6
src/rtos/embKernel.c
View File

@ -83,7 +83,7 @@ struct embKernel_params {
struct embKernel_params embKernel_params_list[] = { struct embKernel_params embKernel_params_list[] = {
{ {
"cortex_m3", /* target_name */ "cortex_m", /* target_name */
4, /* pointer_width */ 4, /* pointer_width */
4, /* thread_count_width */ 4, /* thread_count_width */
8, /*rtos_list_size */ 8, /*rtos_list_size */
@ -93,7 +93,7 @@ struct embKernel_params embKernel_params_list[] = {
4, /*thread_priority_width */ 4, /*thread_priority_width */
4, /*iterable_next_offset */ 4, /*iterable_next_offset */
12, /*iterable_task_owner_offset */ 12, /*iterable_task_owner_offset */
&rtos_embkernel_Cortex_M3_stacking, /* stacking_info*/ &rtos_embkernel_Cortex_M_stacking, /* stacking_info*/
}, },
{ "hla_target", /* target_name */ { "hla_target", /* target_name */
4, /* pointer_width */ 4, /* pointer_width */
@ -105,7 +105,7 @@ struct embKernel_params embKernel_params_list[] = {
4, /*thread_priority_width */ 4, /*thread_priority_width */
4, /*iterable_next_offset */ 4, /*iterable_next_offset */
12, /*iterable_task_owner_offset */ 12, /*iterable_task_owner_offset */
&rtos_embkernel_Cortex_M3_stacking, /* stacking_info */ &rtos_embkernel_Cortex_M_stacking, /* stacking_info */
} }
}; };

6
src/rtos/rtos_embkernel_stackings.c
View File

@ -24,7 +24,7 @@
#include "rtos.h" #include "rtos.h"
static const struct stack_register_offset rtos_embkernel_Cortex_M3_stack_offsets[] = { static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[] = {
{ 0x24, 32 }, /* r0 */ { 0x24, 32 }, /* r0 */
{ 0x28, 32 }, /* r1 */ { 0x28, 32 }, /* r1 */
{ 0x2c, 32 }, /* r2 */ { 0x2c, 32 }, /* r2 */
@ -53,12 +53,12 @@ static const struct stack_register_offset rtos_embkernel_Cortex_M3_stack_offsets
{ 0x40, 32 }, /* xPSR */ { 0x40, 32 }, /* xPSR */
}; };
const struct rtos_register_stacking rtos_embkernel_Cortex_M3_stacking = { const struct rtos_register_stacking rtos_embkernel_Cortex_M_stacking = {
0x40, /* stack_registers_size */ 0x40, /* stack_registers_size */
-1, /* stack_growth_direction */ -1, /* stack_growth_direction */
26, /* num_output_registers */ 26, /* num_output_registers */
8, /* stack_alignment */ 8, /* stack_alignment */
rtos_embkernel_Cortex_M3_stack_offsets /* register_offsets */ rtos_embkernel_Cortex_M_stack_offsets /* register_offsets */
}; };

2
src/rtos/rtos_embkernel_stackings.h
View File

@ -27,6 +27,6 @@
#include "rtos.h" #include "rtos.h"
extern const struct rtos_register_stacking rtos_embkernel_Cortex_M3_stacking; extern const struct rtos_register_stacking rtos_embkernel_Cortex_M_stacking;
#endif /* ifndef INCLUDED_RTOS_EMBKERNEL_STACKINGS_H_ */ #endif /* ifndef INCLUDED_RTOS_EMBKERNEL_STACKINGS_H_ */

8
src/target/armv7m.c
View File

@ -602,7 +602,7 @@ int armv7m_checksum_memory(struct target *target,
/* see contrib/loaders/checksum/armv7m_crc.s for src */ /* see contrib/loaders/checksum/armv7m_crc.s for src */
static const uint8_t cortex_m3_crc_code[] = { static const uint8_t cortex_m_crc_code[] = {
/* main: */ /* main: */
0x02, 0x46, /* mov r2, r0 */ 0x02, 0x46, /* mov r2, r0 */
0x00, 0x20, /* movs r0, #0 */ 0x00, 0x20, /* movs r0, #0 */
@ -636,12 +636,12 @@ int armv7m_checksum_memory(struct target *target,
0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */ 0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */
}; };
retval = target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm); retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = target_write_buffer(target, crc_algorithm->address, retval = target_write_buffer(target, crc_algorithm->address,
sizeof(cortex_m3_crc_code), (uint8_t *)cortex_m3_crc_code); sizeof(cortex_m_crc_code), (uint8_t *)cortex_m_crc_code);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto cleanup; goto cleanup;
@ -657,7 +657,7 @@ int armv7m_checksum_memory(struct target *target,
int timeout = 20000 * (1 + (count / (1024 * 1024))); int timeout = 20000 * (1 + (count / (1024 * 1024)));
retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6), crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6),
timeout, &armv7m_info); timeout, &armv7m_info);
if (retval == ERROR_OK) if (retval == ERROR_OK)

597
src/target/cortex_m.c
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File diff suppressed because it is too large Load Diff

66
src/target/cortex_m.h
View File

@ -24,12 +24,12 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/ ***************************************************************************/
#ifndef CORTEX_M3_H #ifndef CORTEX_M_H
#define CORTEX_M3_H #define CORTEX_M_H
#include "armv7m.h" #include "armv7m.h"
#define CORTEX_M3_COMMON_MAGIC 0x1A451A45 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
#define SYSTEM_CONTROL_BASE 0x400FE000 #define SYSTEM_CONTROL_BASE 0x400FE000
@ -135,14 +135,14 @@
#define FPCR_REPLACE_BKPT_HIGH (2 << 30) #define FPCR_REPLACE_BKPT_HIGH (2 << 30)
#define FPCR_REPLACE_BKPT_BOTH (3 << 30) #define FPCR_REPLACE_BKPT_BOTH (3 << 30)
struct cortex_m3_fp_comparator { struct cortex_m_fp_comparator {
int used; int used;
int type; int type;
uint32_t fpcr_value; uint32_t fpcr_value;
uint32_t fpcr_address; uint32_t fpcr_address;
}; };
struct cortex_m3_dwt_comparator { struct cortex_m_dwt_comparator {
int used; int used;
uint32_t comp; uint32_t comp;
uint32_t mask; uint32_t mask;
@ -150,18 +150,18 @@ struct cortex_m3_dwt_comparator {
uint32_t dwt_comparator_address; uint32_t dwt_comparator_address;
}; };
enum cortex_m3_soft_reset_config { enum cortex_m_soft_reset_config {
CORTEX_M3_RESET_SYSRESETREQ, CORTEX_M_RESET_SYSRESETREQ,
CORTEX_M3_RESET_VECTRESET, CORTEX_M_RESET_VECTRESET,
}; };
enum cortex_m3_isrmasking_mode { enum cortex_m_isrmasking_mode {
CORTEX_M3_ISRMASK_AUTO, CORTEX_M_ISRMASK_AUTO,
CORTEX_M3_ISRMASK_OFF, CORTEX_M_ISRMASK_OFF,
CORTEX_M3_ISRMASK_ON, CORTEX_M_ISRMASK_ON,
}; };
struct cortex_m3_common { struct cortex_m_common {
int common_magic; int common_magic;
struct arm_jtag jtag_info; struct arm_jtag jtag_info;
@ -176,39 +176,39 @@ struct cortex_m3_common {
int fp_code_available; int fp_code_available;
int fpb_enabled; int fpb_enabled;
int auto_bp_type; int auto_bp_type;
struct cortex_m3_fp_comparator *fp_comparator_list; struct cortex_m_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */ /* Data Watchpoint and Trace (DWT) */
int dwt_num_comp; int dwt_num_comp;
int dwt_comp_available; int dwt_comp_available;
struct cortex_m3_dwt_comparator *dwt_comparator_list; struct cortex_m_dwt_comparator *dwt_comparator_list;
struct reg_cache *dwt_cache; struct reg_cache *dwt_cache;
enum cortex_m3_soft_reset_config soft_reset_config; enum cortex_m_soft_reset_config soft_reset_config;
enum cortex_m3_isrmasking_mode isrmasking_mode; enum cortex_m_isrmasking_mode isrmasking_mode;
struct armv7m_common armv7m; struct armv7m_common armv7m;
}; };
static inline struct cortex_m3_common * static inline struct cortex_m_common *
target_to_cm3(struct target *target) target_to_cm(struct target *target)
{ {
return container_of(target->arch_info, return container_of(target->arch_info,
struct cortex_m3_common, armv7m); struct cortex_m_common, armv7m);
} }
int cortex_m3_examine(struct target *target); int cortex_m_examine(struct target *target);
int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint); int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint); int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint); int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint); int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint); int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint); int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
void cortex_m3_enable_breakpoints(struct target *target); void cortex_m_enable_breakpoints(struct target *target);
void cortex_m3_enable_watchpoints(struct target *target); void cortex_m_enable_watchpoints(struct target *target);
void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target); void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
#endif /* CORTEX_M3_H */ #endif /* CORTEX_M_H */

32
src/target/hla_target.c
View File

@ -330,14 +330,14 @@ static int hl_handle_target_request(void *priv)
} }
static int adapter_init_arch_info(struct target *target, static int adapter_init_arch_info(struct target *target,
struct cortex_m3_common *cortex_m3, struct cortex_m_common *cortex_m,
struct jtag_tap *tap) struct jtag_tap *tap)
{ {
struct armv7m_common *armv7m; struct armv7m_common *armv7m;
LOG_DEBUG("%s", __func__); LOG_DEBUG("%s", __func__);
armv7m = &cortex_m3->armv7m; armv7m = &cortex_m->armv7m;
armv7m_init_arch_info(target, armv7m); armv7m_init_arch_info(target, armv7m);
armv7m->load_core_reg_u32 = adapter_load_core_reg_u32; armv7m->load_core_reg_u32 = adapter_load_core_reg_u32;
@ -366,12 +366,12 @@ static int adapter_target_create(struct target *target,
{ {
LOG_DEBUG("%s", __func__); LOG_DEBUG("%s", __func__);
struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common)); struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
if (!cortex_m3) if (!cortex_m)
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
adapter_init_arch_info(target, cortex_m3, target->tap); adapter_init_arch_info(target, cortex_m, target->tap);
return ERROR_OK; return ERROR_OK;
} }
@ -619,8 +619,8 @@ static int adapter_resume(struct target *target, int current,
if (!debug_execution) { if (!debug_execution) {
target_free_all_working_areas(target); target_free_all_working_areas(target);
cortex_m3_enable_breakpoints(target); cortex_m_enable_breakpoints(target);
cortex_m3_enable_watchpoints(target); cortex_m_enable_watchpoints(target);
} }
pc = armv7m->arm.pc; pc = armv7m->arm.pc;
@ -660,14 +660,14 @@ static int adapter_resume(struct target *target, int current,
LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
breakpoint->address, breakpoint->address,
breakpoint->unique_id); breakpoint->unique_id);
cortex_m3_unset_breakpoint(target, breakpoint); cortex_m_unset_breakpoint(target, breakpoint);
res = adapter->layout->api->step(adapter->fd); res = adapter->layout->api->step(adapter->fd);
if (res != ERROR_OK) if (res != ERROR_OK)
return res; return res;
cortex_m3_set_breakpoint(target, breakpoint); cortex_m_set_breakpoint(target, breakpoint);
} }
} }
@ -718,7 +718,7 @@ static int adapter_step(struct target *target, int current,
if (handle_breakpoints) { if (handle_breakpoints) {
breakpoint = breakpoint_find(target, pc_value); breakpoint = breakpoint_find(target, pc_value);
if (breakpoint) if (breakpoint)
cortex_m3_unset_breakpoint(target, breakpoint); cortex_m_unset_breakpoint(target, breakpoint);
} }
armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found); armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
@ -743,7 +743,7 @@ static int adapter_step(struct target *target, int current,
register_cache_invalidate(armv7m->arm.core_cache); register_cache_invalidate(armv7m->arm.core_cache);
if (breakpoint) if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint); cortex_m_set_breakpoint(target, breakpoint);
adapter_debug_entry(target); adapter_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED); target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@ -794,7 +794,7 @@ struct target_type hla_target = {
.init_target = adapter_init_target, .init_target = adapter_init_target,
.target_create = adapter_target_create, .target_create = adapter_target_create,
.examine = cortex_m3_examine, .examine = cortex_m_examine,
.commands = adapter_command_handlers, .commands = adapter_command_handlers,
.poll = adapter_poll, .poll = adapter_poll,
@ -819,8 +819,8 @@ struct target_type hla_target = {
.start_algorithm = armv7m_start_algorithm, .start_algorithm = armv7m_start_algorithm,
.wait_algorithm = armv7m_wait_algorithm, .wait_algorithm = armv7m_wait_algorithm,
.add_breakpoint = cortex_m3_add_breakpoint, .add_breakpoint = cortex_m_add_breakpoint,
.remove_breakpoint = cortex_m3_remove_breakpoint, .remove_breakpoint = cortex_m_remove_breakpoint,
.add_watchpoint = cortex_m3_add_watchpoint, .add_watchpoint = cortex_m_add_watchpoint,
.remove_watchpoint = cortex_m3_remove_watchpoint, .remove_watchpoint = cortex_m_remove_watchpoint,
}; };

4
src/target/target.c
View File

@ -87,7 +87,7 @@ extern struct target_type fa526_target;
extern struct target_type feroceon_target; extern struct target_type feroceon_target;
extern struct target_type dragonite_target; extern struct target_type dragonite_target;
extern struct target_type xscale_target; extern struct target_type xscale_target;
extern struct target_type cortexm3_target; extern struct target_type cortexm_target;
extern struct target_type cortexa8_target; extern struct target_type cortexa8_target;
extern struct target_type cortexr4_target; extern struct target_type cortexr4_target;
extern struct target_type arm11_target; extern struct target_type arm11_target;
@ -115,7 +115,7 @@ static struct target_type *target_types[] = {
&feroceon_target, &feroceon_target,
&dragonite_target, &dragonite_target,
&xscale_target, &xscale_target,
&cortexm3_target, &cortexm_target,
&cortexa8_target, &cortexa8_target,
&cortexr4_target, &cortexr4_target,
&arm11_target, &arm11_target,

8
testing/examples/cortex/cm3-ftest.cfg
View File

@ -15,8 +15,8 @@
# + observe fault "handling" -- loop-to-self from load_and_run (below) # + observe fault "handling" -- loop-to-self from load_and_run (below)
# #
# - Test #2: verify that "vector_catch" makes OpenOCD stops ignoring them # - Test #2: verify that "vector_catch" makes OpenOCD stops ignoring them
# + cortex_m3 vector_catch none # + cortex_m vector_catch none
# + cortex_m3 vector_catch VECTOR # + cortex_m vector_catch VECTOR
# + l_VECTOR (loads testcase to RAM) # + l_VECTOR (loads testcase to RAM)
# + fault triggers vector catch hardware # + fault triggers vector catch hardware
# + observe OpenOCD entering debug state with no assistance # + observe OpenOCD entering debug state with no assistance
@ -31,8 +31,8 @@
proc vector_test {tag} { proc vector_test {tag} {
halt halt
# REVISIT -- annoying, we'd like to scrap vector_catch output # REVISIT -- annoying, we'd like to scrap vector_catch output
cortex_m3 vector_catch none cortex_m vector_catch none
cortex_m3 vector_catch $tag cortex_m vector_catch $tag
eval "l_$tag" eval "l_$tag"
} }

18
testing/examples/cortex/fault.c
View File

@ -28,7 +28,7 @@
*/ */
/* These symbols match the OpenOCD "cortex_m3 vector_catch" bit names. */ /* These symbols match the OpenOCD "cortex_m vector_catch" bit names. */
enum vc_case { enum vc_case {
hard_err, hard_err,
int_err, int_err,
@ -71,21 +71,21 @@ int main(void)
*/ */
switch (VC_ID) { switch (VC_ID) {
/* "cortex_m3 vector_catch hard_err" */ /* "cortex_m vector_catch hard_err" */
case hard_err: case hard_err:
/* FORCED - Fault escalation */ /* FORCED - Fault escalation */
/* FIXME code this */ /* FIXME code this */
break; break;
/* "cortex_m3 vector_catch int_err" */ /* "cortex_m vector_catch int_err" */
case int_err: case int_err:
/* STKERR -- Exception stack BusFault */ /* STKERR -- Exception stack BusFault */
/* FIXME code this */ /* FIXME code this */
break; break;
/* "cortex_m3 vector_catch bus_err" */ /* "cortex_m vector_catch bus_err" */
case bus_err: case bus_err:
/* PRECISERR -- precise data bus read /* PRECISERR -- precise data bus read
* Here we assume a Cortex-M3 with 512 MBytes SRAM is very * Here we assume a Cortex-M3 with 512 MBytes SRAM is very
@ -97,13 +97,13 @@ int main(void)
); );
break; break;
/* "cortex_m3 vector_catch state_err" */ /* "cortex_m vector_catch state_err" */
case state_err: case state_err:
/* UNDEFINSTR -- architectural undefined instruction */ /* UNDEFINSTR -- architectural undefined instruction */
__asm__ volatile(".hword 0xde00"); __asm__ volatile(".hword 0xde00");
break; break;
/* "cortex_m3 vector_catch chk_err" */ /* "cortex_m vector_catch chk_err" */
case chk_err: case chk_err:
/* UNALIGNED ldm */ /* UNALIGNED ldm */
__asm__ volatile( __asm__ volatile(
@ -112,7 +112,7 @@ int main(void)
); );
break; break;
/* "cortex_m3 vector_catch nocp_err" */ /* "cortex_m vector_catch nocp_err" */
case nocp_err: case nocp_err:
/* NOCP ... Cortex-M3 has no coprocessors (like CP14 DCC), /* NOCP ... Cortex-M3 has no coprocessors (like CP14 DCC),
* but these instructions are allowed by ARMv7-M. * but these instructions are allowed by ARMv7-M.
@ -120,7 +120,7 @@ int main(void)
__asm__ volatile("mrc p14, 0, r0, c0, c5, 0"); __asm__ volatile("mrc p14, 0, r0, c0, c5, 0");
break; break;
/* "cortex_m3 vector_catch mm_err" */ /* "cortex_m vector_catch mm_err" */
case mm_err: case mm_err:
/* IACCVIOL -- instruction fetch from an XN region */ /* IACCVIOL -- instruction fetch from an XN region */
__asm__ volatile( __asm__ volatile(
@ -129,7 +129,7 @@ int main(void)
); );
break; break;
/* "cortex_m3 vector_catch reset" */ /* "cortex_m vector_catch reset" */
case reset: case reset:
__asm__ volatile( __asm__ volatile(
/* r1 = SYSRESETREQ */ /* r1 = SYSRESETREQ */