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More error reporting in Cortex_a8 execute_opcode 

git-svn-id: svn://svn.berlios.de/openocd/trunk@2793 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
mlu 2009-10-02 16:39:50 +00:00
parent 84dabdcc72
commit 1b90a9f5eb
1 changed files with 6 additions and 0 deletions
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6
src/target/cortex_a8.c
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@ -165,8 +165,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
{
LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
return retval; return retval;
} }
}
while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
@ -176,8 +179,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
{
LOG_ERROR("Could not read DSCR register");
return retval; return retval;
} }
}
while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
return retval; return retval;