flash/nor: Update cc26xx flash driver to support cc13x2x7

This updates the flash driver to support more than one bank.
This is required to support the cc1352p7 which has two banks.

This only have been tested on a cc1352p7.
The loader has been built using a gcc-arm-none-eabi-4_8-2014q3
toolchain.

Change-Id: Ia813421ececd96d6e2fd4dae910ad60fcc3d3c88
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8192
Tested-by: jenkins
Reviewed-by: Vaishnav M A <vaishnav@beagleboard.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Alexandre Bailon 2024-03-29 21:13:17 +01:00 committed by Antonio Borneo
parent d35399b00e
commit 1aa759dbb9
5 changed files with 616 additions and 532 deletions

View File

@ -1,249 +1,248 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */ /* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47, 0x02,0xbc,0x08,0x47,0xab,0x00,0xe3,0x18,0x88,0x22,0x48,0x46,0x98,0x50,0xc4,0x20,
0x00,0x00,0x00,0x00,0x24,0xf2,0xff,0x7f,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x40,0x00,0x22,0x18,0x10,0x68,0x01,0x21,0xa9,0x40,0x08,0x43,0x10,0x60,0x84,0x22,
0x28,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff, 0x52,0x00,0x40,0x46,0x98,0x50,0x02,0x2e,0xdf,0xd1,0xc6,0x22,0x52,0x00,0xa3,0x18,
0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0x18,0x0f,0x00,0x20, 0x18,0x68,0x01,0x43,0x19,0x60,0xd8,0xe7,0x1c,0x1c,0x4d,0x34,0xff,0x34,0x5c,0x51,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x12,0x00,0x20, 0xb3,0xe7,0xc0,0x46,0xfc,0x0e,0x00,0x20,0x00,0x00,0x00,0x00,0xf8,0xb5,0xc0,0x46,
0x6c,0x12,0x00,0x20,0xd4,0x12,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,
0x9e,0x46,0x70,0x47,0x00,0x00,0x00,0x00,0xc8,0xf1,0xff,0x7f,0x01,0x00,0x00,0x00,
0x18,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,
0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0x08,0x0f,0x00,0x20,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf4,0x11,0x00,0x20,
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@ -307,8 +306,9 @@
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View File

@ -1,258 +1,257 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */ /* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb, 0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xff,0xf6,
0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20, 0xfa,0xaf,0x00,0xf0,0x71,0xf9,0xfe,0xe7,0xe8,0x0e,0x00,0x20,0x4c,0x13,0x00,0x20,
0xfc,0x13,0x00,0x20,0x08,0xb5,0x07,0x4b,0x07,0x48,0x03,0x33,0x1b,0x1a,0x06,0x2b, 0xf4,0x13,0x00,0x20,0x10,0xb5,0x07,0x4c,0x23,0x78,0x00,0x2b,0x07,0xd1,0x06,0x4b,
0x04,0xd9,0x06,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,0x5c,0xf8,0x08,0xbc,0x01,0xbc,
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0x0a,0x48,0x03,0x68,0x00,0x2b,0x04,0xd1,0xff,0xf7,0xc2,0xff,0x08,0xbc,0x01,0xbc, 0x08,0x48,0x03,0x68,0x00,0x2b,0x04,0xd0,0x07,0x4b,0x00,0x2b,0x01,0xd0,0x00,0xf0,
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0x0a,0x43,0x94,0x46,0x8a,0x46,0x42,0x46,0x61,0x46,0x11,0x60,0x84,0x22,0x49,0x46, 0x29,0xd3,0x00,0x2f,0xf4,0xd1,0x41,0x46,0x4a,0x68,0x01,0x3a,0x33,0x68,0xa2,0x42,
0x5f,0x46,0x52,0x00,0x8f,0x50,0x02,0x2d,0xbf,0xd1,0x02,0x1c,0x55,0x46,0x8d,0x32, 0x30,0xd0,0x00,0x22,0x32,0x60,0x00,0x2b,0xef,0xd0,0x40,0x46,0x59,0x46,0x40,0x68,
0xff,0x32,0x11,0x68,0x0d,0x43,0x15,0x60,0xb7,0xe7,0x20,0x1c,0x4d,0x30,0xff,0x30, 0x01,0x22,0x09,0x68,0xa2,0x40,0x00,0x90,0x11,0x42,0x20,0xd0,0x50,0x46,0x00,0x68,
0xe0,0x50,0xac,0xe7,0x01,0x20,0x40,0x42,0xb4,0xe7,0xc0,0x46,0x0c,0x0f,0x00,0x20, 0x10,0x42,0x21,0xd1,0x02,0x98,0x29,0x68,0x00,0xf0,0x40,0xf8,0x41,0x46,0x49,0x68,
0x00,0x00,0x00,0x00,0x08,0xb5,0x04,0x4b,0x00,0x2b,0x02,0xd0,0x03,0x48,0xff,0xf7, 0x00,0x9a,0x91,0x42,0xb7,0xd1,0x4a,0x46,0x12,0x68,0x42,0x45,0xb3,0xd1,0x04,0x3d,
0x9b,0xfe,0x08,0xbc,0x01,0xbc,0x00,0x47,0x00,0x00,0x00,0x00,0x15,0x0b,0x00,0x20, 0x04,0x3e,0x01,0x3c,0xd5,0xd2,0x18,0x4a,0x00,0x2a,0x11,0xd1,0x05,0xb0,0x3c,0xbc,
0xf0,0xb5,0x56,0x46,0x5f,0x46,0x4d,0x46,0x44,0x46,0xf0,0xb4,0x0e,0x1c,0x3f,0x4b, 0x90,0x46,0x99,0x46,0xa2,0x46,0xab,0x46,0xf0,0xbc,0x01,0xbc,0x00,0x47,0x00,0xf0,
0x1b,0x68,0x87,0xb0,0x03,0x93,0x49,0x33,0xff,0x33,0x01,0x90,0x04,0x93,0xa4,0x22, 0x25,0xf8,0xe3,0xe7,0x4c,0x60,0xce,0xe7,0x28,0x68,0x00,0xf0,0x1f,0xf8,0xdd,0xe7,
0x03,0x9b,0x52,0x00,0x9f,0x58,0x00,0x2f,0x4d,0xd0,0x04,0x9b,0x98,0x46,0x00,0x23, 0x43,0x46,0x5b,0x68,0x40,0x46,0x00,0x2b,0x0d,0xd1,0x03,0x68,0x00,0x2b,0x0e,0xd0,
0x9b,0x46,0xc4,0x23,0x5b,0x00,0x9c,0x46,0xbc,0x44,0x63,0x46,0x02,0x93,0xc6,0x23, 0x49,0x46,0x0b,0x60,0xaf,0xf3,0x00,0x80,0x4b,0x46,0x1a,0x68,0x90,0x46,0x41,0x46,
0x5b,0x00,0x9a,0x46,0x7c,0x68,0xa5,0x00,0x7d,0x19,0xba,0x44,0x01,0x3c,0x08,0xd5, 0x00,0x29,0x91,0xd1,0xda,0xe7,0x03,0x68,0xc1,0x46,0x98,0x46,0xf7,0xe7,0x00,0x23,
0x27,0xe0,0x6b,0x1d,0xff,0x33,0x1b,0x68,0xb3,0x42,0x04,0xd0,0x04,0x3d,0x01,0x3c, 0xfa,0xe7,0xc0,0x46,0x04,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,
0x1f,0xd3,0x00,0x2e,0xf5,0xd1,0x7b,0x68,0x01,0x3b,0x6a,0x68,0xa3,0x42,0x3e,0xd0, 0x08,0xb5,0x01,0x1c,0x00,0x22,0x00,0x20,0x00,0x23,0x00,0xf0,0x1f,0xf8,0x08,0xbc,
0x5b,0x46,0x6b,0x60,0x00,0x2a,0xf1,0xd0,0x7b,0x68,0x99,0x46,0x01,0x23,0xa3,0x40, 0x02,0xbc,0x08,0x47,0x38,0xb5,0x0a,0x4b,0x0a,0x4d,0xed,0x1a,0xad,0x10,0x0a,0xd0,
0x02,0x99,0x09,0x68,0x05,0x91,0x19,0x42,0x26,0xd1,0x00,0xf0,0x43,0xf8,0x7b,0x68, 0x01,0x3d,0xac,0x00,0xe4,0x18,0x00,0xe0,0x01,0x3d,0x23,0x68,0x00,0xf0,0x0c,0xf8,
0x4b,0x45,0xc4,0xd1,0x43,0x46,0x1b,0x68,0xbb,0x42,0xc0,0xd1,0x04,0x3d,0x01,0x3c, 0x04,0x3c,0x00,0x2d,0xf8,0xd1,0x00,0xf0,0x71,0xf8,0x38,0xbc,0x01,0xbc,0x00,0x47,
0xdf,0xd2,0x1b,0x4b,0x00,0x2b,0x0e,0xd0,0x7b,0x68,0x00,0x2b,0x27,0xd1,0x3b,0x68, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x47,0xc0,0x46,0xf0,0xb5,0x4f,0x46,
0x00,0x2b,0x28,0xd0,0x42,0x46,0x38,0x1c,0x13,0x60,0xaf,0xf3,0x00,0x80,0x43,0x46, 0x46,0x46,0xc0,0xb4,0x98,0x46,0x2c,0x4b,0xa4,0x25,0x1b,0x68,0x6d,0x00,0x5c,0x59,
0x1f,0x68,0x00,0x2f,0xb5,0xd1,0x07,0xb0,0x3c,0xbc,0x90,0x46,0x99,0x46,0xa2,0x46, 0x83,0xb0,0x06,0x1c,0x0f,0x1c,0x91,0x46,0x01,0x93,0x00,0x2c,0x46,0xd0,0x65,0x68,
0xab,0x46,0xf0,0xbc,0x01,0xbc,0x00,0x47,0x51,0x46,0x09,0x68,0x19,0x42,0x08,0xd1, 0x1f,0x2d,0x1a,0xdd,0x25,0x4b,0x00,0x2b,0x02,0xd1,0x01,0x20,0x40,0x42,0x1c,0xe0,
0x2b,0x1c,0x84,0x33,0x19,0x68,0x01,0x98,0x00,0xf0,0x14,0xf8,0xcf,0xe7,0x7c,0x60, 0xc8,0x20,0x40,0x00,0xaf,0xf3,0x00,0x80,0x04,0x1e,0xf6,0xd0,0x00,0x25,0x45,0x60,
0xc0,0xe7,0x2b,0x1c,0x84,0x33,0x18,0x68,0x00,0xf0,0x0c,0xf8,0xc7,0xe7,0x3b,0x68, 0xa4,0x23,0x01,0x98,0x5b,0x00,0xc0,0x58,0x01,0x99,0x20,0x60,0xcc,0x50,0xc4,0x23,
0xb8,0x46,0x1f,0x1c,0xdd,0xe7,0x00,0x23,0xfa,0xe7,0xc0,0x46,0x0c,0x0f,0x00,0x20, 0x5b,0x00,0xe5,0x50,0xc6,0x23,0x5b,0x00,0xe5,0x50,0x00,0x2e,0x0c,0xd1,0x6b,0x1c,
0x00,0x00,0x00,0x00,0x10,0x47,0xc0,0x46,0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc, 0x02,0x35,0xad,0x00,0x63,0x60,0x2f,0x51,0x00,0x20,0x03,0xb0,0x0c,0xbc,0x90,0x46,
0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47, 0x99,0x46,0xf0,0xbc,0x02,0xbc,0x08,0x47,0xab,0x00,0xe3,0x18,0x88,0x22,0x48,0x46,
0x00,0x00,0x00,0x00,0x24,0xf2,0xff,0x7f,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x98,0x50,0xc4,0x20,0x40,0x00,0x22,0x18,0x10,0x68,0x01,0x21,0xa9,0x40,0x08,0x43,
0x8c,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff, 0x10,0x60,0x84,0x22,0x52,0x00,0x40,0x46,0x98,0x50,0x02,0x2e,0xdf,0xd1,0xc6,0x22,
0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,0x43,0x00,0x00,0x00,0x18,0x0f,0x00,0x20, 0x52,0x00,0xa3,0x18,0x18,0x68,0x01,0x43,0x19,0x60,0xd8,0xe7,0x1c,0x1c,0x4d,0x34,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x12,0x00,0x20, 0xff,0x34,0x5c,0x51,0xb3,0xe7,0xc0,0x46,0x04,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,
0x6c,0x12,0x00,0x20,0xd4,0x12,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0xf8,0xb5,0xc0,0x46,0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0xf8,0xb5,0xc0,0x46,
0xf8,0xbc,0x08,0xbc,0x9e,0x46,0x70,0x47,0x00,0x00,0x00,0x00,0xc4,0xf1,0xff,0x7f,
0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x84,0x15,0x00,0x20,0xff,0xff,0xff,0xc5,
0xff,0xff,0xff,0xff,0xc5,0xff,0xff,0xff,0xc5,0xc5,0xc5,0xff,0xc5,0xc5,0xc5,0xff,
0x43,0x00,0x00,0x00,0x10,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0xfc,0x11,0x00,0x20,0x64,0x12,0x00,0x20,0xcc,0x12,0x00,0x20,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x0f,0x00,0x20,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0e,0x33,0xcd,0xab,0x34,0x12,0x6d,0xe6, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0xec,0xde,0x05,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x0e,0x33,0xcd,0xab,0x34,0x12,0x6d,0xe6,0xec,0xde,0x05,0x00,0x0b,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@ -307,8 +306,9 @@
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x18,0x0f,0x00,0x20,0xc1,0x00,0x00,0x20,0x91,0x00,0x00,0x20,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x0f,0x00,0x20,0x61,0x00,0x00,0x20,
0x95,0x0d,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x35,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x6d,0x0c,0x00,0x20,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

View File

@ -42,7 +42,7 @@ typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t);
* *
******************************************************************************/ ******************************************************************************/
static void issue_fsm_command(flash_state_command_t command); static void issue_fsm_command(flash_state_command_t command);
static void enable_sectors_for_write(void); static void enable_sectors_for_write(uint32_t);
static uint32_t scale_cycle_values(uint32_t specified_timing, static uint32_t scale_cycle_values(uint32_t specified_timing,
uint32_t scale_value); uint32_t scale_value);
static void set_write_mode(void); static void set_write_mode(void);
@ -80,42 +80,51 @@ uint32_t flash_bank_erase(bool force_precondition)
uint32_t error_return; uint32_t error_return;
uint32_t sector_address; uint32_t sector_address;
uint32_t reg_val; uint32_t reg_val;
uint32_t bank_no;
uint32_t top_bank_start_addr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) &
FLASH_FCFG_B1_START_B1_START_ADDR_M)
>> FLASH_FCFG_B1_START_B1_START_ADDR_S;
/* Enable all sectors for erase. */ for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
enable_sectors_for_write(); /* Enable all sectors for erase. */
enable_sectors_for_write(bank_no);
/* Clear the Status register. */ /* Clear the Status register. */
issue_fsm_command(FAPI_CLEAR_STATUS); issue_fsm_command(FAPI_CLEAR_STATUS);
/* Enable erase of all sectors and enable precondition if required. */ /* Enable erase of all sectors and enable precondition if required. */
reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
if (force_precondition)
HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
FLASH_FSM_ST_MACHINE_DO_PRECOND;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
/* Issue the bank erase command to the FSM. */
issue_fsm_command(FAPI_ERASE_BANK);
/* Wait for erase to finish. */
while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
;
/* Update status. */
error_return = flash_check_fsm_for_error();
/* Disable sectors for erase. */
flash_disable_sectors_for_write();
/* Set configured precondition mode since it may have been forced on. */
if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
~FLASH_FSM_ST_MACHINE_DO_PRECOND; HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
if (force_precondition)
HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
FLASH_FSM_ST_MACHINE_DO_PRECOND;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
// Write address to FADDR register.
HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (bank_no * top_bank_start_addr);
/* Issue the bank erase command to the FSM. */
issue_fsm_command(FAPI_ERASE_BANK);
/* Wait for erase to finish. */
while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
;
/* Update status. */
error_return = flash_check_fsm_for_error();
/* Set configured precondition mode since it may have been forced on. */
if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
~FLASH_FSM_ST_MACHINE_DO_PRECOND;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
}
if (error_return != FAPI_STATUS_SUCCESS)
break;
} }
/* Program security data to default values in the customer configuration */ /* Program security data to default values in the customer configuration */
@ -128,6 +137,9 @@ uint32_t flash_bank_erase(bool force_precondition)
CCFG_SIZE_SECURITY); CCFG_SIZE_SECURITY);
} }
/* Disable sectors for erase. */
flash_disable_sectors_for_write();
/* Return status of operation. */ /* Return status of operation. */
return error_return; return error_return;
} }
@ -161,23 +173,34 @@ uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count)
******************************************************************************/ ******************************************************************************/
void flash_disable_sectors_for_write(void) void flash_disable_sectors_for_write(void)
{ {
uint32_t bank_no;
/* Configure flash back to read mode */ /* Configure flash back to read mode */
set_read_mode(); set_read_mode();
/* Disable Level 1 Protection. */ for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
/* Disable all sectors for erase and programming. */ /* Select flash bank. */
HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
/* Enable Level 1 Protection. */ /* Disable Level 1 Protection. */
HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
/* Protect sectors from sector erase. */ /* Disable all sectors for erase and programming. */
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; /* Enable Level 1 Protection. */
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
/* Protect sectors from sector erase. */
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
}
// Select bank 0
HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0;
} }
/****************************************************************************** /******************************************************************************
@ -214,7 +237,7 @@ static void issue_fsm_command(flash_state_command_t command)
* the FLASH_O_FSM_SECTOR1 register. * the FLASH_O_FSM_SECTOR1 register.
* *
******************************************************************************/ ******************************************************************************/
static void enable_sectors_for_write(void) static void enable_sectors_for_write(uint32_t bank_no)
{ {
/* Trim flash module for program/erase operation. */ /* Trim flash module for program/erase operation. */
trim_for_write(); trim_for_write();
@ -223,7 +246,7 @@ static void enable_sectors_for_write(void)
set_write_mode(); set_write_mode();
/* Select flash bank. */ /* Select flash bank. */
HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
/* Disable Level 1 Protection. */ /* Disable Level 1 Protection. */
HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;

View File

@ -246,6 +246,46 @@ static inline uint32_t flash_check_fsm_for_ready(void)
return FAPI_STATUS_FSM_READY; return FAPI_STATUS_FSM_READY;
} }
/******************************************************************************
*
* Get the number of banks
*
* This function returns the number of bank of the flash.
*
* Returns the number of banks
*
******************************************************************************/
static inline uint32_t flash_bank_count(void)
{
uint32_t bank_count;
bank_count = (HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
FLASH_FCFG_BANK_MAIN_NUM_BANK_M) >>
FLASH_FCFG_BANK_MAIN_NUM_BANK_S;
return bank_count;
}
/******************************************************************************
*
* Get the size of the bank.
*
* This function returns the size of the main bank in number of bytes.
*
* Returns the flash size in number of bytes.
*
******************************************************************************/
static inline uint8_t flash_bank_width(void)
{
uint8_t bank_width;
bank_width = (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >>
FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3);
return bank_width;
}
/****************************************************************************** /******************************************************************************
* *
* Erase a flash sector. * Erase a flash sector.

View File

@ -116,6 +116,10 @@
/* FMC Sequential Pump Information */ /* FMC Sequential Pump Information */
#define FLASH_O_FSEQPMP 0x000020A8 #define FLASH_O_FSEQPMP 0x000020A8
#define FLASH_O_FADDR 0x00002110
#define FLASH_O_FWPWRITE0 0x00002120
/* FMC FSM Command */ /* FMC FSM Command */
#define FLASH_O_FSM_CMD 0x0000220C #define FLASH_O_FSM_CMD 0x0000220C
@ -179,9 +183,14 @@
/* FMC FSM Sector Erased 2 */ /* FMC FSM Sector Erased 2 */
#define FLASH_O_FSM_SECTOR2 0x000022C4 #define FLASH_O_FSM_SECTOR2 0x000022C4
#define FLASH_O_FCFG_BANK 0x00002400
/* FMC Flash Bank 0 Starting Address */ /* FMC Flash Bank 0 Starting Address */
#define FLASH_O_FCFG_B0_START 0x00002410 #define FLASH_O_FCFG_B0_START 0x00002410
/* FMC Flash Bank 1 Starting Address */
#define FLASH_O_FCFG_B1_START 0x00002414
/* FMC Flash Bank 0 Sector Size 0 */ /* FMC Flash Bank 0 Sector Size 0 */
#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 #define FLASH_O_FCFG_B0_SSIZE0 0x00002430
@ -1353,4 +1362,16 @@
* 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */ * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 #define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002
/* Field: [3:0] MAIN_NUM_BANK */
#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F
#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0
/* Field: [23:0] B1_START_ADDR */
#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF
#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0
/* Field: [15:4] MAIN_BANK_WIDTH */
#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0
#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4
#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */ #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */