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cortex a8: add missing error handling for mem_ap_read_atomic_u32() 

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe 2010-07-18 23:01:16 +02:00
parent d10f0def80
commit 19fc52f008
1 changed files with 11 additions and 0 deletions
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11
src/target/cortex_a8.c
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@ -11,6 +11,9 @@
* Copyright (C) 2009 by Dirk Behme * * Copyright (C) 2009 by Dirk Behme *
* dirk.behme@gmail.com - copy from cortex_m3 * * dirk.behme@gmail.com - copy from cortex_m3 *
* * * *
* Copyright (C) 2010 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify * * This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by * * it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or * * the Free Software Foundation; either version 2 of the License, or *
@ -228,6 +231,8 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
{ {
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
} }
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
@ -251,6 +256,8 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* Check that DCCRX is not full */ /* Check that DCCRX is not full */
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr); armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if (dscr & DSCR_DTR_RX_FULL) if (dscr & DSCR_DTR_RX_FULL)
{ {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
@ -352,10 +359,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR, a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr); &dscr);
if (retval != ERROR_OK)
return retval;
} }
retval = mem_ap_read_atomic_u32(swjdp, retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
//LOG_DEBUG("read DCC 0x%08" PRIx32, *data); //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
if (dscr_p) if (dscr_p)