tcl/target/renesas_rz_g2: Added RZ/G2LC and RZ/G2UL
Added support for two new devices: RZ/G2LC and RZ/G2UL Change-Id: Iec6ba88c1d279f50808b060343b45c796bbfdbfc Signed-off-by: micbis <michele.bisogno.ct@renesas.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6972 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -6,11 +6,13 @@
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# - Each SOC can boot through the Cortex-A5x cores
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# - Each SOC can boot through the Cortex-A5x cores
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# Supported RZ/G2 SOCs and their cores:
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# Supported RZ/G2 SOCs and their cores:
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# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
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# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
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# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
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# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
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# RZ/G2N: Cortex-A57 x2, Cortex-R7
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# RZ/G2N: Cortex-A57 x2, Cortex-R7
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# RZ/G2E: Cortex-A53 x2, Cortex-R7
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# RZ/G2E: Cortex-A53 x2, Cortex-R7
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# RZ/G2L: Cortex-A55 x2, Cortex-M33
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# RZ/G2L: Cortex-A55 x2, Cortex-M33
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# RZ/G2LC: Cortex-A55 x2, Cortex-M33
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# RZ/G2UL: Cortex-A55 x1, Cortex-M33
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# Usage:
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# Usage:
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# There are 2 configuration options:
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# There are 2 configuration options:
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@ -75,6 +77,20 @@ switch $_soc {
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set _boot_core CA55
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set _boot_core CA55
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set _ap_num 0
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set _ap_num 0
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}
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}
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G2LC {
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set _CHIPNAME r9a07g044c
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set _num_ca55 2
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set _num_cm33 1
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set _boot_core CA55
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set _ap_num 0
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}
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G2UL {
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set _CHIPNAME r9a07g043u
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set _num_ca55 1
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set _num_cm33 1
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set _boot_core CA55
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set _ap_num 0
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}
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default {
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default {
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error "'$_soc' is invalid!"
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error "'$_soc' is invalid!"
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}
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}
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@ -169,7 +185,7 @@ if { $_boot_core == "CA57" } {
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echo "SMP targets:$smp_targets"
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echo "SMP targets:$smp_targets"
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eval "target smp $smp_targets"
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eval "target smp $smp_targets"
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if { $_soc == "G2L"} {
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if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } {
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target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
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target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
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}
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}
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