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target: aarch64: access reg SPSR_EL1 only in EL1, EL2 and EL3 

The register SPSR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.

Without this patch, an error:
	Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
        x/p $SPSR_EL1
or through OpenOCD command
        reg SPSR_EL1

Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.

Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8276
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2024-05-14 14:40:07 +02:00
parent b5dfef7577
commit 198fecf5e4
1 changed files with 15 additions and 7 deletions
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22
src/target/armv8.c
View File

@ -369,9 +369,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64); ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64);
break; break;
case ARMV8_SPSR_EL1: case ARMV8_SPSR_EL1:
retval = dpm->instr_read_data_r0(dpm, if (curel < SYSTEM_CUREL_EL1) {
ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value); LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
value_64 = value; retval = ERROR_FAIL;
break;
}
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value_64);
break; break;
case ARMV8_SPSR_EL2: case ARMV8_SPSR_EL2:
if (curel < SYSTEM_CUREL_EL2) { if (curel < SYSTEM_CUREL_EL2) {
@ -526,9 +530,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64); ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64);
break; break;
case ARMV8_SPSR_EL1: case ARMV8_SPSR_EL1:
value = value_64; if (curel < SYSTEM_CUREL_EL1) {
retval = dpm->instr_write_data_r0(dpm, LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value); retval = ERROR_FAIL;
break;
}
retval = dpm->instr_write_data_r0_64(dpm,
ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value_64);
break; break;
case ARMV8_SPSR_EL2: case ARMV8_SPSR_EL2:
if (curel < SYSTEM_CUREL_EL2) { if (curel < SYSTEM_CUREL_EL2) {
@ -1582,7 +1590,7 @@ static const struct {
NULL}, NULL},
{ ARMV8_ESR_EL1, "ESR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked", { ARMV8_ESR_EL1, "ESR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL}, NULL},
{ ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked", { ARMV8_SPSR_EL1, "SPSR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL}, NULL},
{ ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked", { ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",