Use algorithm to speed up fespi flash programming.
It's still really slow, at 854b/s, but it seems to work and it's a lot of new code. Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
This commit is contained in:
Tim Newsome
parent
6686e71bd6
commit
18eedf996c
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@ -41,6 +41,7 @@
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#include "spi.h"
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#include <jtag/jtag.h>
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#include <helper/time_support.h>
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#include <target/algorithm.h>
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/* Register offsets */
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@ -357,27 +358,16 @@ static int fespi_protect(struct flash_bank *bank, int set,
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return ERROR_OK;
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}
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/* This should write something less than or equal to a page.*/
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static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t len)
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static int slow_fespi_write_buffer(struct flash_bank *bank,
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const uint8_t *buffer, uint32_t offset, uint32_t len)
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{
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struct target *target = bank->target;
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t ctrl_base = fespi_info->ctrl_base;
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uint32_t ii;
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//TODO!!! assert that len < page size
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LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
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__func__, offset, len);
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printf("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
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__func__, offset, len);
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fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
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fespi_txwm_wait(bank);
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@ -400,6 +390,102 @@ static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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return ERROR_OK;
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}
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/* This should write something less than or equal to a page.*/
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static int fespi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t chip_offset, uint32_t len,
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struct working_area *algorithm_wa)
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{
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struct target *target = bank->target;
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t ctrl_base = fespi_info->ctrl_base;
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LOG_DEBUG("%s: chip_offset=0x%08" PRIx32 " len=0x%08" PRIx32,
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__func__, chip_offset, len);
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if (!algorithm_wa) {
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return slow_fespi_write_buffer(bank, buffer, chip_offset, len);
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}
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struct working_area *data_wa;
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unsigned data_wa_size = len + 4;
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while (1) {
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if (data_wa_size < 128) {
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LOG_WARNING("Couldn't allocate data working area.");
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return slow_fespi_write_buffer(bank, buffer, chip_offset, len);
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}
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if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
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ERROR_OK) {
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break;
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}
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data_wa_size /= 2;
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}
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fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
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fespi_txwm_wait(bank);
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FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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// Make the biggest possible block of txdata so we can write it in the
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// minimum number of operations.
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uint8_t *tx_data = malloc(4 + len);
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if (!tx_data) {
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LOG_ERROR("Couldn't allocate tx_data.");
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return ERROR_FAIL;
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}
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tx_data[0] = SPIFLASH_PAGE_PROGRAM;
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tx_data[1] = chip_offset >> 16;
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tx_data[2] = chip_offset >> 8;
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tx_data[3] = chip_offset;
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memcpy(tx_data + 4, buffer, len);
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len += 4;
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struct reg_param reg_params[3];
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init_reg_param(®_params[0], "x10", 32, PARAM_OUT);
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init_reg_param(®_params[1], "x11", 32, PARAM_OUT);
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init_reg_param(®_params[2], "x12", 32, PARAM_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, ctrl_base + FESPI_REG_TXFIFO);
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buf_set_u32(reg_params[1].value, 0, 32, data_wa->address);
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unsigned offset = 0;
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while (len > 0) {
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unsigned bytes = MIN(len, data_wa->size);
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buf_set_u32(reg_params[2].value, 0, 32, bytes);
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int retval = target_write_buffer(target, data_wa->address, bytes,
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tx_data + offset);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to write data to 0x%x: %d", data_wa->address,
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retval);
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goto error;
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}
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retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
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algorithm_wa->address,
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algorithm_wa->address + algorithm_wa->size - 4,
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10000, NULL);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to execute algorithm at 0x%x: %d", algorithm_wa->address,
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retval);
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goto error;
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}
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len -= bytes;
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offset += bytes;
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}
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target_free_working_area(target, data_wa);
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fespi_txwm_wait(bank);
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FESPI_WRITE_REG(FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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return ERROR_OK;
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error:
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target_free_working_area(target, data_wa);
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LOG_ERROR("Falling back to slow write.");
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return slow_fespi_write_buffer(bank, buffer, chip_offset, len);
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}
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static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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@ -436,6 +522,39 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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}
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}
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struct working_area *algorithm_wa;
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static const uint32_t riscv_write_buffer_code[] = {
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// a0 - address of FESPI_REG_TXFIFO
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// a1 - start address of buffer
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// a2 - size of buffer, in bytes
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/* 0 */ 0x00052283, // lw t0,0(a0)
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/* 4 */ 0xfe02cee3, // bltz t0,0
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/* 8 */ 0x00058283, // lb t0,0(a1)
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/* c */ 0x00552023, // sw t0,0(a0)
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/* 10 */ 0x00158593, // addi a1,a1,1
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/* 14 */ 0xfff60613, // addi a2,a2,-1
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/* 18 */ 0xfec044e3, // bgtz a2,0
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/* 1c */ 0x00100073, // ebreak
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};
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if (target_alloc_working_area(target, sizeof(riscv_write_buffer_code),
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&algorithm_wa) != ERROR_OK) {
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LOG_WARNING("Couldn't allocate %ld-byte working area.",
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sizeof(riscv_write_buffer_code));
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algorithm_wa = NULL;
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} else {
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uint8_t code[sizeof(riscv_write_buffer_code)];
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target_buffer_set_u32_array(target, code,
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ARRAY_SIZE(riscv_write_buffer_code), riscv_write_buffer_code);
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retval = target_write_buffer(target, algorithm_wa->address,
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sizeof(code), code);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to write code to 0x%x: %d", algorithm_wa->address,
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retval);
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target_free_working_area(target, algorithm_wa);
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algorithm_wa = NULL;
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}
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}
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page_size = fespi_info->dev->pagesize;
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fespi_txwm_wait(bank);
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@ -454,7 +573,7 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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if (cur_count > count)
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cur_count = count;
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retval = fespi_write_buffer(bank, buffer, offset,
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cur_count);
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cur_count, algorithm_wa);
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if (retval != ERROR_OK)
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goto err;
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offset += cur_count;
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@ -472,7 +591,7 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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cur_count = count & ~3;
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retval = fespi_write_buffer(bank, buffer, offset,
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cur_count);
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cur_count, algorithm_wa);
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if (retval != ERROR_OK)
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goto err;
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@ -486,9 +605,13 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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/* buffer tail */
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if (count > 0)
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retval = fespi_write_buffer(bank, buffer, offset, count);
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retval = fespi_write_buffer(bank, buffer, offset, count, algorithm_wa);
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err:
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if (algorithm_wa) {
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target_free_working_area(target, algorithm_wa);
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}
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/* Switch to HW mode before return to prompt */
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FESPI_ENABLE_HW_MODE();
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return retval;
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@ -7,12 +7,14 @@
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#endif
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#include "target.h"
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#include "target/algorithm.h"
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#include "target_type.h"
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#include "log.h"
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#include "jtag/jtag.h"
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#include "opcodes.h"
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#include "register.h"
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#include "breakpoints.h"
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#include "helper/time_support.h"
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/**
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* Since almost everything can be accomplish by scanning the dbus register, all
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@ -1291,6 +1293,7 @@ static int register_get(struct reg *reg)
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return ERROR_OK;
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} else if (reg->number == REG_PC) {
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buf_set_u32(reg->value, 0, 32, info->dpc);
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reg->valid = true;
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LOG_DEBUG("%s=0x%" PRIx64 " (cached)", reg->name, info->dpc);
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return ERROR_OK;
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} else if (reg->number >= REG_FPR0 && reg->number <= REG_FPR31) {
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@ -2628,11 +2631,114 @@ static int riscv_get_gdb_reg_list(struct target *target,
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return ERROR_OK;
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}
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int riscv_arch_state(struct target *target)
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static int riscv_arch_state(struct target *target)
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{
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return ERROR_OK;
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}
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// Algorithm must end with a software breakpoint instruction.
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static int riscv_run_algorithm(struct target *target, int num_mem_params,
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struct mem_param *mem_params, int num_reg_params,
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struct reg_param *reg_params, uint32_t entry_point,
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uint32_t exit_point, int timeout_ms, void *arch_info)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (num_mem_params > 0) {
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LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
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return ERROR_FAIL;
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}
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if (target->state != TARGET_HALTED) {
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/// Save registers
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if (register_get(&target->reg_cache->reg_list[REG_PC]) != ERROR_OK) {
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return ERROR_FAIL;
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}
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uint64_t saved_pc = reg_cache_get(target, REG_PC);
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uint64_t saved_regs[32];
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for (int i = 0; i < num_reg_params; i++) {
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LOG_DEBUG("save %s", reg_params[i].reg_name);
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struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
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if (!r) {
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LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
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return ERROR_FAIL;
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}
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if (r->size != reg_params[i].size) {
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LOG_ERROR("Register %s is %d bits instead of %d bits.",
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reg_params[i].reg_name, r->size, reg_params[i].size);
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return ERROR_FAIL;
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}
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if (r->number > REG_XPR31) {
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LOG_ERROR("Only GPRs can be use as argument registers.");
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return ERROR_FAIL;
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}
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if (register_get(r) != ERROR_OK) {
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return ERROR_FAIL;
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}
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saved_regs[r->number] = buf_get_u64(r->value, 0, info->xlen);
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if (register_set(r, reg_params[i].value) != ERROR_OK) {
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return ERROR_FAIL;
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}
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}
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/// Run algorithm
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LOG_DEBUG("resume at 0x%x", entry_point);
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if (riscv_resume(target, 0, entry_point, 0, 0) != ERROR_OK) {
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return ERROR_FAIL;
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}
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int64_t start = timeval_ms();
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while (target->state != TARGET_HALTED) {
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LOG_DEBUG("poll()");
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int64_t now = timeval_ms();
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if (now - start > timeout_ms) {
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LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
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return ERROR_TARGET_TIMEOUT;
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}
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int result = riscv_poll(target);
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if (result != ERROR_OK) {
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return result;
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}
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}
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if (register_get(&target->reg_cache->reg_list[REG_PC]) != ERROR_OK) {
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return ERROR_FAIL;
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}
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uint64_t final_pc = reg_cache_get(target, REG_PC);
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if (final_pc != exit_point) {
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LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%" PRIx32,
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final_pc, exit_point);
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return ERROR_FAIL;
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}
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/// Restore registers
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uint8_t buf[8];
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buf_set_u64(buf, 0, info->xlen, saved_pc);
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if (register_set(&target->reg_cache->reg_list[REG_PC], buf) != ERROR_OK) {
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return ERROR_FAIL;
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}
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for (int i = 0; i < num_reg_params; i++) {
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LOG_DEBUG("restore %s", reg_params[i].reg_name);
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struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
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buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
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if (register_set(r, buf) != ERROR_OK) {
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return ERROR_FAIL;
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}
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}
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return ERROR_OK;
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}
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struct target_type riscv_target =
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{
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.name = "riscv",
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@ -2663,4 +2769,6 @@ struct target_type riscv_target =
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.remove_watchpoint = riscv_remove_watchpoint,
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.arch_state = riscv_arch_state,
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.run_algorithm = riscv_run_algorithm,
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};
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