interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cortex_a: Add support for A7 MPCore 

A7 MPCore needs unlocking the debug registers same as with A15 MPCore.
Found out by hacking on the code.

Change-Id: I613cb4fb35007b85b4a9a401577b47768bc1a08b
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-on: http://openocd.zylin.com/2344
Tested-by: jenkins
Reviewed-by: Kamal Dasu <kamal.dasu@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Alexander Stein 2014-10-14 11:55:27 +02:00 committed by Andreas Fritiofson
parent e519099ab7
commit 1567caea2c
2 changed files with 14 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/target/cortex_a.c
View File

@ -208,6 +208,7 @@ static int cortex_a_init_debug_access(struct target *target)
CORTEX_A_MIDR_PARTNUM_SHIFT; CORTEX_A_MIDR_PARTNUM_SHIFT;
switch (cortex_part_num) { switch (cortex_part_num) {
case CORTEX_A7_PARTNUM:
case CORTEX_A15_PARTNUM: case CORTEX_A15_PARTNUM:
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLSR, armv7a->debug_base + CPUDBG_OSLSR,
@ -2511,6 +2512,18 @@ static int cortex_a_examine_first(struct target *target)
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
}
/* Unlocking the debug registers */
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A7_PARTNUM) {
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
if (retval != ERROR_OK)
return retval;
} }
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);

1
src/target/cortex_a.h
View File

@ -35,6 +35,7 @@
#define CORTEX_A_COMMON_MAGIC 0x411fc082 #define CORTEX_A_COMMON_MAGIC 0x411fc082
#define CORTEX_A15_COMMON_MAGIC 0x413fc0f1 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
#define CORTEX_A7_PARTNUM 0xc07
#define CORTEX_A8_PARTNUM 0xc08 #define CORTEX_A8_PARTNUM 0xc08
#define CORTEX_A9_PARTNUM 0xc09 #define CORTEX_A9_PARTNUM 0xc09
#define CORTEX_A15_PARTNUM 0xc0f #define CORTEX_A15_PARTNUM 0xc0f