Proofreading, typo and grammar fixes to Ch 10 User's Guide.
Various cleanups to Chapter 10 of the User's Guide, no functional changes. Change-Id: I055d032eacc8e85b1d8edbd4bcc505f6f0feaa49 Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-on: http://openocd.zylin.com/1861 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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Robert P. J. Day
Spencer Oliver
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@ -3593,7 +3593,7 @@ It then invokes the logic of @command{jtag arp_init}.
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TAPs serve many roles, including:
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@itemize @bullet
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@item @b{Debug Target} A CPU TAP can be used as a GDB debug target
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@item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
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@item @b{Flash Programming} Some chips program the flash directly via JTAG.
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Others do it indirectly, making a CPU do it.
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@item @b{Program Download} Using the same CPU support GDB uses,
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@ -3601,7 +3601,7 @@ you can initialize a DRAM controller, download code to DRAM, and then
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start running that code.
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@item @b{Boundary Scan} Most chips support boundary scan, which
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helps test for board assembly problems like solder bridges
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and missing connections
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and missing connections.
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@end itemize
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OpenOCD must know about the active TAPs on your board(s).
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@ -3614,7 +3614,7 @@ probes flash memory, performs low-level JTAG operations, and more.
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@cindex scan chain
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TAPs are part of a hardware @dfn{scan chain},
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which is daisy chain of TAPs.
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which is a daisy chain of TAPs.
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They also need to be added to
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OpenOCD's software mirror of that hardware list,
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giving each member a name and associating other data with it.
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@ -3642,7 +3642,7 @@ Here's what the scan chain might look like for a chip more than one TAP:
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OpenOCD can detect some of that information, but not all
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of it. @xref{autoprobing,,Autoprobing}.
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Unfortunately those TAPs can't always be autoconfigured,
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Unfortunately, those TAPs can't always be autoconfigured,
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because not all devices provide good support for that.
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JTAG doesn't require supporting IDCODE instructions, and
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chips with JTAG routers may not link TAPs into the chain
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@ -3662,8 +3662,8 @@ by a given chip.
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Board configuration files combine all the targets on a board,
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and so forth.
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Note that @emph{the order in which TAPs are declared is very important.}
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It must match the order in the JTAG scan chain, both inside
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a single chip and between them.
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That declaration order must match the order in the JTAG scan chain,
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both inside a single chip and between them.
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@xref{faqtaporder,,FAQ TAP Order}.
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For example, the ST Microsystems STR912 chip has
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@ -3680,9 +3680,9 @@ jtag newtap str912 cpu ... params ...
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jtag newtap str912 bs ... params ...
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@end example
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Actual config files use a variable instead of literals like
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@option{str912}, to support more than one chip of each type.
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@xref{Config File Guidelines}.
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Actual config files typically use a variable such as @code{$_CHIPNAME}
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instead of literals like @option{str912}, to support more than one chip
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of each type. @xref{Config File Guidelines}.
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@deffn Command {jtag names}
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Returns the names of all current TAPs in the scan chain.
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@ -3754,19 +3754,19 @@ The @var{tapname} reflects the role of that TAP,
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and should follow this convention:
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@itemize @bullet
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@item @code{bs} -- For boundary scan if this is a seperate TAP;
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@item @code{bs} -- For boundary scan if this is a separate TAP;
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@item @code{cpu} -- The main CPU of the chip, alternatively
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@code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
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@code{arm1} and @code{arm2} on chips two ARMs, and so forth;
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@code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
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@item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
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@item @code{flash} -- If the chip has a flash TAP, like the str912;
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@item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
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@item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
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on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
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@item @code{tap} -- Should be used only FPGA or CPLD like devices
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@item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
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with a single TAP;
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@item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
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@item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
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For example, the Freescale IMX31 has a SDMA (Smart DMA) with
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For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
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a JTAG TAP; that TAP should be named @code{sdma}.
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@end itemize
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@ -3783,12 +3783,12 @@ A TAP may also provide optional @var{configparams}:
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@itemize @bullet
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@item @code{-disable} (or @code{-enable})
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@*Use the @code{-disable} parameter to flag a TAP which is not
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linked in to the scan chain after a reset using either TRST
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linked into the scan chain after a reset using either TRST
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or the JTAG state machine's @sc{reset} state.
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You may use @code{-enable} to highlight the default state
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(the TAP is linked in).
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@xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
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@item @code{-expected-id} @var{number}
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@item @code{-expected-id} @var{NUMBER}
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@*A non-zero @var{number} represents a 32-bit IDCODE
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which you expect to find when the scan chain is examined.
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These codes are not required by all JTAG devices.
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@ -3815,7 +3815,7 @@ on entry to the @sc{ircapture} state, such as 0x01.
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JTAG requires the two LSBs of this value to be 01.
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By default, @code{-ircapture} and @code{-irmask} are set
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up to verify that two-bit value. You may provide
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additional bits, if you know them, or indicate that
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additional bits if you know them, or indicate that
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a TAP doesn't conform to the JTAG specification.
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@item @code{-irmask} @var{NUMBER}
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@*A mask used with @code{-ircapture}
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@ -3827,8 +3827,8 @@ there seems to be no problems with JTAG scan chain operations.
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@section Other TAP commands
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@deffn Command {jtag cget} dotted.name @option{-event} name
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@deffnx Command {jtag configure} dotted.name @option{-event} name string
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@deffn Command {jtag cget} dotted.name @option{-event} event_name
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@deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
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At this writing this TAP attribute
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mechanism is used only for event handling.
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(It is not a direct analogue of the @code{cget}/@code{configure}
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@ -3876,7 +3876,7 @@ implement @command{jtag tapenable}
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by issuing the relevant JTAG commands.
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@end itemize
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If you need some action after each JTAG reset, which isn't actually
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If you need some action after each JTAG reset which isn't actually
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specific to any TAP (since you can't yet trust the scan chain's
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contents to be accurate), you might:
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@ -3895,8 +3895,8 @@ jtag configure CHIP.jrc -event post-reset @{
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In some systems, a @dfn{JTAG Route Controller} (JRC)
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is used to enable and/or disable specific JTAG TAPs.
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Many ARM based chips from Texas Instruments include
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an ``ICEpick'' module, which is a JRC.
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Many ARM-based chips from Texas Instruments include
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an ``ICEPick'' module, which is a JRC.
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Such chips include DaVinci and OMAP3 processors.
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A given TAP may not be visible until the JRC has been
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