jtag/vdebug: add support for DAP6
This change implements the support for the ARM Debug Interface v6. The DAP-level interface properly selects the DP Banks and AP address. Sample ARM configuration DAP and JTAG scripts have been updated. Change-Id: I7df87ef764bca587697c778810443649a7f46c2b Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8067 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Jacek Wuwer
Antonio Borneo
parent
80b970bd29
commit
151b743714
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@ -53,7 +53,7 @@
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#include "helper/log.h"
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#include "helper/list.h"
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#define VD_VERSION 47
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#define VD_VERSION 48
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#define VD_BUFFER_LEN 4024
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#define VD_CHEADER_LEN 24
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#define VD_SHEADER_LEN 16
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@ -66,7 +66,8 @@
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* @brief List of transactor types
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*/
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enum {
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VD_BFM_JTDP = 0x0001, /* transactor DAP JTAG DP */
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VD_BFM_TPIU = 0x0000, /* transactor trace TPIU */
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VD_BFM_DAP6 = 0x0001, /* transactor DAP ADI V6 */
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VD_BFM_SWDP = 0x0002, /* transactor DAP SWD DP */
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VD_BFM_AHB = 0x0003, /* transactor AMBA AHB */
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VD_BFM_APB = 0x0004, /* transactor AMBA APB */
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@ -467,14 +468,14 @@ static int vdebug_run_reg_queue(int hsock, struct vd_shm *pm, unsigned int count
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for (unsigned int j = 0; j < num; j++)
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memcpy(&data[j * awidth], &pm->rd8[(rwords + j) * awidth], awidth);
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}
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LOG_DEBUG_IO("read %04x AS:%02x RG:%02x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
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aspace, addr, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
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LOG_DEBUG("read %04x AS:%1x RG:%1x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
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aspace, addr << 2, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
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(num ? le_to_h_u32(&pm->rd8[rwords * 4]) : 0xdead));
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rwords += num * wwidth;
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waddr += sizeof(uint64_t) / 4; /* waddr past header */
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} else {
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LOG_DEBUG_IO("write %04x AS:%02x RG:%02x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
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aspace, addr, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
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LOG_DEBUG("write %04x AS:%1x RG:%1x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
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aspace, addr << 2, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
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le_to_h_u32(&pm->wd8[(waddr + num + 1) * 4]));
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waddr += sizeof(uint64_t) / 4 + (num * wwidth * awidth + 3) / 4;
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}
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@ -518,7 +519,7 @@ static int vdebug_open(int hsock, struct vd_shm *pm, const char *path,
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rc = VD_ERR_VERSION;
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} else {
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pm->cmd = VD_CMD_CONNECT;
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pm->type = type; /* BFM type to connect to, here JTAG */
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pm->type = type; /* BFM type to connect to */
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h_u32_to_le(pm->rwdata, sig_mask | VD_SIG_BUF | (VD_SIG_BUF << 16));
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h_u16_to_le(pm->wbytes, strlen(path) + 1);
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h_u16_to_le(pm->rbytes, 12);
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@ -922,7 +923,7 @@ static int vdebug_reset(int trst, int srst)
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static int vdebug_jtag_tms_seq(const uint8_t *tms, int num, uint8_t f_flush)
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{
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LOG_INFO("tms len:%d tms:%x", num, *tms);
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LOG_DEBUG_IO("tms len:%d tms:%x", num, *tms);
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return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num, *tms, 0, NULL, 0, 0, NULL, f_flush);
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}
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@ -930,7 +931,7 @@ static int vdebug_jtag_tms_seq(const uint8_t *tms, int num, uint8_t f_flush)
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static int vdebug_jtag_path_move(struct pathmove_command *cmd, uint8_t f_flush)
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{
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uint8_t tms[DIV_ROUND_UP(cmd->num_states, 8)];
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LOG_INFO("path num states %d", cmd->num_states);
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LOG_DEBUG_IO("path num states %d", cmd->num_states);
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memset(tms, 0, DIV_ROUND_UP(cmd->num_states, 8));
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@ -950,7 +951,7 @@ static int vdebug_jtag_tlr(tap_state_t state, uint8_t f_flush)
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tap_state_t cur = tap_get_state();
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uint8_t tms_pre = tap_get_tms_path(cur, state);
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uint8_t num_pre = tap_get_tms_path_len(cur, state);
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LOG_INFO("tlr from %x to %x", cur, state);
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LOG_DEBUG_IO("tlr from %x to %x", cur, state);
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if (cur != state) {
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rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, 0, NULL, 0, 0, NULL, f_flush);
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tap_set_state(state);
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@ -970,7 +971,7 @@ static int vdebug_jtag_scan(struct scan_command *cmd, uint8_t f_flush)
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uint8_t tms_post = tap_get_tms_path(state, cmd->end_state);
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uint8_t num_post = tap_get_tms_path_len(state, cmd->end_state);
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int num_bits = jtag_scan_size(cmd);
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LOG_DEBUG("scan len:%d fields:%d ir/!dr:%d state cur:%x end:%x",
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LOG_DEBUG_IO("scan len:%d fields:%d ir/!dr:%d state cur:%x end:%x",
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num_bits, cmd->num_fields, cmd->ir_scan, cur, cmd->end_state);
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for (int i = 0; i < cmd->num_fields; i++) {
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uint8_t cur_num_pre = i == 0 ? num_pre : 0;
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@ -996,7 +997,7 @@ static int vdebug_jtag_runtest(int cycles, tap_state_t state, uint8_t f_flush)
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tap_state_t cur = tap_get_state();
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uint8_t tms_pre = tap_get_tms_path(cur, state);
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uint8_t num_pre = tap_get_tms_path_len(cur, state);
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LOG_DEBUG("idle len:%d state cur:%x end:%x", cycles, cur, state);
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LOG_DEBUG_IO("idle len:%d state cur:%x end:%x", cycles, cur, state);
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int rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, cycles, NULL, 0, 0, NULL, f_flush);
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if (cur != state)
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tap_set_state(state);
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@ -1006,7 +1007,7 @@ static int vdebug_jtag_runtest(int cycles, tap_state_t state, uint8_t f_flush)
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static int vdebug_jtag_stableclocks(int num, uint8_t f_flush)
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{
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LOG_INFO("stab len:%d state cur:%x", num, tap_get_state());
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LOG_DEBUG("stab len:%d state cur:%x", num, tap_get_state());
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return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, 0, 0, num, NULL, 0, 0, NULL, f_flush);
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}
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@ -1081,6 +1082,41 @@ static int vdebug_jtag_execute_queue(void)
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return rc;
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}
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static int vdebug_dap_bankselect(struct adiv5_ap *ap, unsigned int reg)
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{
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int rc = ERROR_OK;
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uint64_t sel;
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if (is_adiv6(ap->dap)) {
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sel = ap->ap_num | (reg & 0x00000FF0);
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if (sel != (ap->dap->select & ~0xfull)) {
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sel |= ap->dap->select & DP_SELECT_DPBANK;
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if (ap->dap->asize > 32)
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sel |= (DP_SELECT1 >> 4) & DP_SELECT_DPBANK;
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ap->dap->select = sel;
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ap->dap->select_valid = true;
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rc = vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, (uint32_t)sel, VD_ASPACE_DP, 0);
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if (rc == ERROR_OK) {
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ap->dap->select_valid = true;
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if (ap->dap->asize > 32)
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rc = vdebug_reg_write(vdc.hsocket, pbuf, (DP_SELECT1 & DP_SELECT_DPBANK) >> 2,
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(uint32_t)(sel >> 32), VD_ASPACE_DP, 0);
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if (rc == ERROR_OK)
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ap->dap->select1_valid = true;
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}
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}
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} else { /* ADIv5 */
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sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
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if (sel != ap->dap->select) {
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ap->dap->select = sel;
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rc = vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, (uint32_t)sel, VD_ASPACE_DP, 0);
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if (rc == ERROR_OK)
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ap->dap->select_valid = true;
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}
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}
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return rc;
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}
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static int vdebug_dap_connect(struct adiv5_dap *dap)
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{
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return dap_dp_init(dap);
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@ -1093,20 +1129,29 @@ static int vdebug_dap_send_sequence(struct adiv5_dap *dap, enum swd_special_seq
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static int vdebug_dap_queue_dp_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data)
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{
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if (reg != DP_SELECT && reg != DP_RDBUFF
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&& (!dap->select_valid || ((reg >> 4) & DP_SELECT_DPBANK) != (dap->select & DP_SELECT_DPBANK))) {
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dap->select = (dap->select & ~DP_SELECT_DPBANK) | ((reg >> 4) & DP_SELECT_DPBANK);
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vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, dap->select, VD_ASPACE_DP, 0);
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dap->select_valid = true;
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}
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return vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_DP, 0);
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}
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static int vdebug_dap_queue_dp_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data)
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{
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if (reg != DP_SELECT && reg != DP_RDBUFF
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&& (!dap->select_valid || ((reg >> 4) & DP_SELECT_DPBANK) != (dap->select & DP_SELECT_DPBANK))) {
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dap->select = (dap->select & ~DP_SELECT_DPBANK) | ((reg >> 4) & DP_SELECT_DPBANK);
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vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, dap->select, VD_ASPACE_DP, 0);
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dap->select_valid = true;
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}
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return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_DP, 0);
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}
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static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data)
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{
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if ((reg & ADIV5_DP_SELECT_APBANK) != ap->dap->select) {
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vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & ADIV5_DP_SELECT_APBANK, VD_ASPACE_DP, 0);
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ap->dap->select = reg & ADIV5_DP_SELECT_APBANK;
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}
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vdebug_dap_bankselect(ap, reg);
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vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, NULL, VD_ASPACE_AP, 0);
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@ -1115,11 +1160,7 @@ static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint3
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static int vdebug_dap_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data)
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{
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if ((reg & ADIV5_DP_SELECT_APBANK) != ap->dap->select) {
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vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & ADIV5_DP_SELECT_APBANK, VD_ASPACE_DP, 0);
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ap->dap->select = reg & ADIV5_DP_SELECT_APBANK;
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}
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vdebug_dap_bankselect(ap, reg);
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return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_AP, 0);
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}
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@ -1175,7 +1216,7 @@ COMMAND_HANDLER(vdebug_set_bfm)
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break;
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}
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if (transport_is_dapdirect_swd())
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vdc.bfm_type = VD_BFM_SWDP;
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vdc.bfm_type = strstr(vdc.bfm_path, "dap6") ? VD_BFM_DAP6 : VD_BFM_SWDP;
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else
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vdc.bfm_type = VD_BFM_JTAG;
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LOG_DEBUG("bfm_path: %s clk_period %ups", vdc.bfm_path, vdc.bfm_period);
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@ -4,10 +4,13 @@
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source [find interface/vdebug.cfg]
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set _CORES 2
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set _CHIPNAME a53
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set _MEMSTART 0x00000000
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set _MEMSIZE 0x1000000
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set CORES 2
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set CHIPNAME a53
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set ACCESSPORT 0
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set MEMSTART 0x00000000
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set MEMSIZE 0x1000000
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set DBGBASE {0x80810000 0x80910000}
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set CTIBASE {0x80820000 0x80920000}
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# vdebug select transport
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transport select dapdirect_swd
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@ -19,11 +22,9 @@ adapter srst delay 5
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# BFM hierarchical path and input clk period
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vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
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# DMA Memories to access backdoor (up to 4)
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vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
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# DMA Memories to access backdoor (up to 20)
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vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
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source [find target/swj-dp.tcl]
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
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swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
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source [find target/vd_aarch64.cfg]
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@ -4,11 +4,14 @@
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source [find interface/vdebug.cfg]
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set _CORES 2
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set _CHIPNAME a53
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set _MEMSTART 0x00000000
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set _MEMSIZE 0x1000000
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set _CPUTAPID 0x5ba00477
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set CORES 2
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set CHIPNAME a53
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set ACCESSPORT 0
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set MEMSTART 0x00000000
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set MEMSIZE 0x1000000
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set DBGBASE {0x80810000 0x80910000}
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set CTIBASE {0x80820000 0x80920000}
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set CPUTAPID 0x5ba00477
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# vdebug select transport
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transport select jtag
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@ -21,11 +24,10 @@ adapter srst delay 5
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# BFM hierarchical path and input clk period
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vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
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# DMA Memories to access backdoor (up to 4)
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vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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# DMA Memories to access backdoor (up to 20)
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vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
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jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
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jtag arp_init-reset
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source [find target/vd_aarch64.cfg]
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@ -0,0 +1,30 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Cadence virtual debug interface
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# Arm Cortex A53x2 through DAP
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source [find interface/vdebug.cfg]
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set CORES 4
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set CHIPNAME a75
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set ACCESSPORT 0x00040000
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set MEMSTART 0x00000000
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set MEMSIZE 0x1000000
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set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
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set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
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# vdebug select transport
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transport select dapdirect_swd
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# JTAG reset config, frequency and reset delay
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adapter speed 200000
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adapter srst delay 5
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# BFM hierarchical path and input clk period
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vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
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# DMA Memories to access backdoor (up to 20)
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#vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
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swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
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source [find target/vd_aarch64.cfg]
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@ -0,0 +1,30 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Cadence virtual debug interface
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# Arm Cortex A53x2 through DAP
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source [find interface/vdebug.cfg]
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set CORES 4
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set CHIPNAME a75
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set ACCESSPORT 0x00040000
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set MEMSTART 0x00000000
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set MEMSIZE 0x1000000
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set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
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set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
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set CPUTAPID 0x4ba06477
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# vdebug select transport
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transport select jtag
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# JTAG reset config, frequency and reset delay
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reset_config trst_and_srst
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adapter speed 1500000
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adapter srst delay 5
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# BFM hierarchical path and input clk period
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vdebug bfm_path tbench.u_vd_jtag_bfm 333ps
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jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
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jtag arp_init-reset
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source [find target/vd_aarch64.cfg]
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@ -4,9 +4,9 @@
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source [find interface/vdebug.cfg]
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set _CHIPNAME m4
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set _MEMSTART 0x00000000
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set _MEMSIZE 0x10000
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set CHIPNAME m4
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set MEMSTART 0x00000000
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set MEMSIZE 0x10000
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# vdebug select transport
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transport select dapdirect_swd
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@ -16,11 +16,9 @@ adapter srst delay 5
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# BFM hierarchical path and input clk period
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vdebug bfm_path tbench.u_vd_swdp_bfm 20ns
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|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
|
||||
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
|
||||
source [find target/vd_cortex_m.cfg]
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CHIPNAME m4
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x10000
|
||||
set _CPUTAPID 0x4ba00477
|
||||
set CHIPNAME m4
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x10000
|
||||
set CPUTAPID 0x4ba00477
|
||||
|
||||
# vdebug select transport
|
||||
transport select jtag
|
||||
|
|
@ -20,11 +20,10 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
|
||||
jtag arp_init-reset
|
||||
|
||||
source [find target/vd_cortex_m.cfg]
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CHIPNAME m7
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x100000
|
||||
set _CPUTAPID 0x0ba02477
|
||||
set CHIPNAME m7
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x100000
|
||||
set CPUTAPID 0x0ba02477
|
||||
|
||||
# vdebug select JTAG transport
|
||||
transport select jtag
|
||||
|
|
@ -20,11 +20,10 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $MEMSTART $MEMSIZE
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
|
||||
jtag arp_init-reset
|
||||
|
||||
source [find target/vd_cortex_m.cfg]
|
||||
|
|
|
|||
|
|
@ -2,36 +2,44 @@
|
|||
# Cadence virtual debug interface
|
||||
# Arm v8 64b Cortex A
|
||||
|
||||
if {![info exists _CORES]} {
|
||||
set _CORES 1
|
||||
if {![info exists CORES]} {
|
||||
set CORES 1
|
||||
}
|
||||
if {![info exists _CHIPNAME]} {
|
||||
set _CHIPNAME aarch64
|
||||
if {![info exists CHIPNAME]} {
|
||||
set CHIPNAME aarch64
|
||||
}
|
||||
if {[info exists ACCESSPORT]} {
|
||||
set _APNUM "-ap-num $ACCESSPORT"
|
||||
if { $ACCESSPORT > 0xff } {
|
||||
set _DAP6 "-adiv6"
|
||||
} else {
|
||||
set _DAP6 "-adiv5"
|
||||
}
|
||||
} else {
|
||||
set _APNUM ""
|
||||
}
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
set _CTINAME $_CHIPNAME.cti
|
||||
|
||||
set DBGBASE {0x80810000 0x80910000}
|
||||
set CTIBASE {0x80820000 0x80920000}
|
||||
set _TARGETNAME $CHIPNAME.cpu
|
||||
set _CTINAME $CHIPNAME.cti
|
||||
set _DAPNAME $CHIPNAME.dap
|
||||
|
||||
dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
|
||||
$_CHIPNAME.dap apsel 1
|
||||
dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME
|
||||
|
||||
for { set _core 0 } { $_core < $_CORES } { incr _core } \
|
||||
for { set _core 0 } { $_core < $CORES } { incr _core } \
|
||||
{
|
||||
cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
|
||||
set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
|
||||
-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
|
||||
set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]"
|
||||
eval $_cmd
|
||||
set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
|
||||
if { $_core != 0 } {
|
||||
# non-boot core examination may fail
|
||||
set _command "$_command -defer-examine"
|
||||
set _smp_command "$_smp_command $_TARGETNAME.$_core"
|
||||
set _cmd "$_cmd -defer-examine"
|
||||
set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core"
|
||||
} else {
|
||||
set _smp_command "target smp $_TARGETNAME.$_core"
|
||||
set _smp_cmd "target smp $_TARGETNAME.$_core"
|
||||
}
|
||||
eval $_command
|
||||
eval $_cmd
|
||||
}
|
||||
eval $_smp_command
|
||||
eval $_smp_cmd
|
||||
|
||||
# default target is core 0
|
||||
targets $_TARGETNAME.0
|
||||
set _TARGETCUR $_TARGETNAME.0
|
||||
targets $_TARGETCUR
|
||||
|
|
|
|||
|
|
@ -2,11 +2,12 @@
|
|||
# Cadence virtual debug interface
|
||||
# ARM Cortex M
|
||||
|
||||
if {![info exists _CHIPNAME]} {
|
||||
set _CHIPNAME cortex_m
|
||||
if {![info exists CHIPNAME]} {
|
||||
set CHIPNAME cortex_m
|
||||
}
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
set _TARGETNAME $CHIPNAME.cpu
|
||||
set _DAPNAME $CHIPNAME.dap
|
||||
|
||||
dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
|
||||
dap create $_DAPNAME -chain-position $_TARGETNAME
|
||||
|
||||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
||||
target create $_TARGETNAME cortex_m -dap $_DAPNAME
|
||||
|
|
|
|||
Loading…
Reference in New Issue