diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c index 96144b64f..d8813756d 100644 --- a/src/target/riscv/batch.c +++ b/src/target/riscv/batch.c @@ -159,7 +159,7 @@ uint32_t riscv_batch_get_dmi_read_data(struct riscv_batch *batch, size_t key) assert(index <= batch->used_scans); uint8_t *base = batch->data_in + DMI_SCAN_BUF_SIZE * index; /* extract "data" field from the DMI read result */ - return (uint32_t)buf_get_u32(base, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH); + return buf_get_u32(base, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH); } void riscv_batch_add_nop(struct riscv_batch *batch) diff --git a/src/target/riscv/program.c b/src/target/riscv/program.c index 59bd52fa9..8e2ce5dbd 100644 --- a/src/target/riscv/program.c +++ b/src/target/riscv/program.c @@ -58,8 +58,8 @@ int riscv_program_exec(struct riscv_program *p, struct target *t) if (riscv_program_ebreak(p) != ERROR_OK) { LOG_ERROR("Unable to write ebreak"); for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i) - LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i, - (long)p->debug_buffer[i], (long)p->debug_buffer[i]); + LOG_ERROR("ram[%02x]: DASM(0x%08" PRIx32 ") [0x%08" PRIx32 "]", + (int)i, p->debug_buffer[i], p->debug_buffer[i]); return ERROR_FAIL; } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 0432c5a40..901e49121 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1561,8 +1561,8 @@ static int discover_vlenb(struct target *target, int hartid) riscv_reg_t vlenb; if (register_read(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK) { - LOG_WARNING("Couldn't read vlenb for %s; vector register access won't " - "work.", target_name(target)); + LOG_WARNING("Couldn't read vlenb for %s; vector register access won't work.", + target_name(target)); r->vlenb[hartid] = 0; return ERROR_OK; } @@ -4149,7 +4149,7 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins return ERROR_FAIL; dm->progbuf_cache[index] = data; } else { - LOG_DEBUG("cache hit for 0x%x @%d", data, index); + LOG_DEBUG("cache hit for 0x%" PRIx32 " @%d", data, index); } return ERROR_OK; }