target: xscale more human vector catching
Replace hexadecimal masks for vector catching with words representing the caught exception, such as dabt for data abort, etc ... This way, the new xscale command is : - xscale vector_catch Reads back to the user the current vector catching status - xscale vector_catch reset dabt pabt Sets the caught vectors to data abort and prefetch abort for example. This is mostly taken from Cortex-M3 openocd code. Change-Id: I66591d5796f0e07f0f31edc8d28722e1e48aa8c5 Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-on: http://openocd.zylin.com/1456 Tested-by: jenkins Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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@ -3218,28 +3218,66 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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static const struct {
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char name[15];
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unsigned mask;
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} vec_ids[] = {
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{ "fiq", DCSR_TF, },
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{ "irq", DCSR_TI, },
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{ "dabt", DCSR_TD, },
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{ "pabt", DCSR_TA, },
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{ "swi", DCSR_TS, },
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{ "undef", DCSR_TU, },
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{ "reset", DCSR_TR, },
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};
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COMMAND_HANDLER(xscale_handle_vector_catch_command)
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COMMAND_HANDLER(xscale_handle_vector_catch_command)
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{
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{
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struct target *target = get_current_target(CMD_CTX);
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struct target *target = get_current_target(CMD_CTX);
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struct xscale_common *xscale = target_to_xscale(target);
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struct xscale_common *xscale = target_to_xscale(target);
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int retval;
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int retval;
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uint32_t dcsr_value;
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uint32_t catch = 0;
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struct reg *dcsr_reg = &xscale->reg_cache->reg_list[XSCALE_DCSR];
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retval = xscale_verify_pointer(CMD_CTX, xscale);
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retval = xscale_verify_pointer(CMD_CTX, xscale);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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if (CMD_ARGC < 1)
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dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
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if (CMD_ARGC > 0) {
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if (CMD_ARGC == 1) {
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if (strcmp(CMD_ARGV[0], "all") == 0) {
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catch = DCSR_TRAP_MASK;
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CMD_ARGC--;
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} else if (strcmp(CMD_ARGV[0], "none") == 0) {
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catch = 0;
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CMD_ARGC--;
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}
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}
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while (CMD_ARGC-- > 0) {
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unsigned i;
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for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
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if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name))
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continue;
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catch |= vec_ids[i].mask;
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break;
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}
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if (i == ARRAY_SIZE(vec_ids)) {
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LOG_ERROR("No vector '%s'", CMD_ARGV[CMD_ARGC]);
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return ERROR_COMMAND_SYNTAX_ERROR;
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return ERROR_COMMAND_SYNTAX_ERROR;
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else {
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}
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COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
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}
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buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value,
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*(uint32_t *)(dcsr_reg->value) &= ~DCSR_TRAP_MASK;
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16,
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*(uint32_t *)(dcsr_reg->value) |= catch;
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8,
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xscale->vector_catch);
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xscale_write_dcsr(target, -1, -1);
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xscale_write_dcsr(target, -1, -1);
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}
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}
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command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch);
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dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
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for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
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command_print(CMD_CTX, "%15s: %s", vec_ids[i].name,
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(dcsr_value & vec_ids[i].mask) ? "catch" : "ignore");
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}
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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@ -3585,9 +3623,9 @@ static const struct command_registration xscale_exec_command_handlers[] = {
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.name = "vector_catch",
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.name = "vector_catch",
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.handler = xscale_handle_vector_catch_command,
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.handler = xscale_handle_vector_catch_command,
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.mode = COMMAND_EXEC,
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.mode = COMMAND_EXEC,
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.help = "set or display 8-bit mask of vectors "
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.help = "set or display mask of vectors "
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"that should trigger debug entry",
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"that should trigger debug entry",
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.usage = "[mask]",
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.usage = "['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']",
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},
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},
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{
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{
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.name = "vector_table",
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.name = "vector_table",
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@ -176,4 +176,15 @@ enum {
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#define ERROR_XSCALE_NO_TRACE_DATA (-700)
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#define ERROR_XSCALE_NO_TRACE_DATA (-700)
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/* DCSR bit and field definitions */
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#define DCSR_TR (1 << 16)
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#define DCSR_TU (1 << 17)
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#define DCSR_TS (1 << 18)
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#define DCSR_TA (1 << 19)
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#define DCSR_TD (1 << 20)
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#define DCSR_TI (1 << 22)
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#define DCSR_TF (1 << 23)
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#define DCSR_TRAP_MASK \
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(DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
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#endif /* XSCALE_H */
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#endif /* XSCALE_H */
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