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cortex_a: drop cortex_a_dap_write_memap_register_u32() 

Historically, the function cortex_a_dap_write_memap_register_u32()
was used to discriminate the register write in APB-AP CPU debug
against the complex memory access in AHB-AP memory bus.

It has no sense to keep the function and its comment.
Plus, by forcing atomic write it impacts the debug performance.

Drop it!
A further rework to enqueue sequence of atomic writes is needed.

Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8231
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2024-05-04 19:13:51 +02:00
parent caabdd4a66
commit 126d8a0972
1 changed files with 39 additions and 52 deletions
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91
src/target/cortex_a.c
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@ -314,19 +314,6 @@ static int cortex_a_exec_opcode(struct target *target,
return retval; return retval;
} }
/* Write to memory mapped registers directly with no cache or mmu handling */
static int cortex_a_dap_write_memap_register_u32(struct target *target,
uint32_t address,
uint32_t value)
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
return retval;
}
/* /*
* Cortex-A implementation of Debug Programmer's Model * Cortex-A implementation of Debug Programmer's Model
* *
@ -611,11 +598,11 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
LOG_DEBUG("A: bpwp enable, vr %08x cr %08x", LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr); (unsigned) vr, (unsigned) cr);
retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target, retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap,
vr, addr); vr, addr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target, retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap,
cr, control); cr, control);
return retval; return retval;
} }
@ -641,7 +628,7 @@ static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr); LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
/* clear control register */ /* clear control register */
return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0); return mem_ap_write_atomic_u32(a->armv7a_common.debug_ap, cr, 0);
} }
static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr) static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
@ -1323,13 +1310,13 @@ static int cortex_a_set_breakpoint(struct target *target,
brp_list[brp_i].used = true; brp_list[brp_i].used = true;
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control; brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value); brp_list[brp_i].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control); brp_list[brp_i].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1415,13 +1402,13 @@ static int cortex_a_set_context_breakpoint(struct target *target,
brp_list[brp_i].used = true; brp_list[brp_i].used = true;
brp_list[brp_i].value = (breakpoint->asid); brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control; brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value); brp_list[brp_i].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control); brp_list[brp_i].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1481,13 +1468,13 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
brp_list[brp_1].used = true; brp_list[brp_1].used = true;
brp_list[brp_1].value = (breakpoint->asid); brp_list[brp_1].value = (breakpoint->asid);
brp_list[brp_1].control = control_ctx; brp_list[brp_1].control = control_ctx;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn,
brp_list[brp_1].value); brp_list[brp_1].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn,
brp_list[brp_1].control); brp_list[brp_1].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1499,13 +1486,13 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
brp_list[brp_2].used = true; brp_list[brp_2].used = true;
brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_2].control = control_iva; brp_list[brp_2].control = control_iva;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn,
brp_list[brp_2].value); brp_list[brp_2].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn,
brp_list[brp_2].control); brp_list[brp_2].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1538,13 +1525,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_i].used = false; brp_list[brp_i].used = false;
brp_list[brp_i].value = 0; brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0; brp_list[brp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control); brp_list[brp_i].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value); brp_list[brp_i].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1557,13 +1544,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_j].used = false; brp_list[brp_j].used = false;
brp_list[brp_j].value = 0; brp_list[brp_j].value = 0;
brp_list[brp_j].control = 0; brp_list[brp_j].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn,
brp_list[brp_j].control); brp_list[brp_j].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn,
brp_list[brp_j].value); brp_list[brp_j].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1582,13 +1569,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_i].used = false; brp_list[brp_i].used = false;
brp_list[brp_i].value = 0; brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0; brp_list[brp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control); brp_list[brp_i].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value); brp_list[brp_i].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1783,14 +1770,14 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
wrp_list[wrp_i].value = address; wrp_list[wrp_i].value = address;
wrp_list[wrp_i].control = control; wrp_list[wrp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn, armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].value); wrp_list[wrp_i].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn, armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].control); wrp_list[wrp_i].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -1832,13 +1819,13 @@ static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *w
wrp_list[wrp_i].used = false; wrp_list[wrp_i].used = false;
wrp_list[wrp_i].value = 0; wrp_list[wrp_i].value = 0;
wrp_list[wrp_i].control = 0; wrp_list[wrp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn, armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].control); wrp_list[wrp_i].control);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn, armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].value); wrp_list[wrp_i].value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;