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doc/openocd.texi: fix bad aarch64 merge 

The documentation added for commit b3d29cb544
was merged after the end of the eSi-RISC section rather than AARCH64.
This patch relocates this hunk to the correct location.

Change-Id: I46a2d24442556e9e8000b46a5e1af03b83de6d98
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/5181
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion 2019-05-21 11:29:27 -07:00 committed by Matthias Welwarsky
parent af952850b5
commit 11e5f02276
1 changed files with 9 additions and 9 deletions
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18
doc/openocd.texi
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@ -9190,6 +9190,14 @@ Selects whether interrupts will be processed when single stepping. The default c
@option{on}.
@end deffn
@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
Cause @command{$target_name} to halt when an exception is taken. Any combination of
Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
@command{$target_name} will halt before taking the exception. In order to resume
the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
Issuing the command without options prints the current configuration.
@end deffn
@section EnSilica eSi-RISC Architecture
eSi-RISC is a highly configurable microprocessor architecture for embedded systems
@ -9333,7 +9341,7 @@ collection.
@deffn Command {esirisc trace init}
Initialize trace collection. This command must be called any time the
configuration changes. If an trace buffer has been configured, the contents will
configuration changes. If a trace buffer has been configured, the contents will
be overwritten when trace collection starts.
@end deffn
@ -9367,14 +9375,6 @@ be copied to an in-memory buffer identified by the @option{address} and
@option{size} options using DMA.
@end deffn
@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
Cause @command{$target_name} to halt when an exception is taken. Any combination of
Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
@command{$target_name} will halt before taking the exception. In order to resume
the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
Issuing the command without options prints the current configuration.
@end deffn
@section Intel Architecture
Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32