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David Brownell <david-b@pacbell.net>: 

DM6446 config updates:

 - List two more TAPs, as disabled, mostly for doc purposes
 - Included basic ICEpick support, still disabled by default
 - Shorten line lengths
 - Use $_TARGETNAME to configure the ETM and ETB
 - This ARM core don't support endianness overriding

For now, boards that can't jumper EMU0/EMU1 will need to tweak
a variable's setting.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2265 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch 2009-06-17 06:40:58 +00:00
parent d31e57a10d
commit 10e435c961
1 changed files with 31 additions and 18 deletions
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49
tcl/target/ti_dm6446.cfg
View File

@ -6,19 +6,28 @@ if { [info exists CHIPNAME] } {
} else { } else {
set _CHIPNAME dm6446 set _CHIPNAME dm6446
} }
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
# #
# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
# are enabled without making ICEpick route ARM and ETB into the JTAG chain. # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
# Override by setting EMU01 to "-disable".
# #
# Also note: when running without RTCK before the PLLs are set up, you # Also note: when running without RTCK before the PLLs are set up, you
# may need to slow the JTAG clock down quite a lot (under 2 MHz). # may need to slow the JTAG clock down quite a lot (under 2 MHz).
# #
source [find target/icepick.cfg]
set EMU01 ""
#set EMU01 "-disable"
# Subsidiary TAP: unknown ... must enable via ICEpick
jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
jtag configure $_CHIPNAME.unknown -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
jtag configure $_CHIPNAME.dsp -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 2"
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID ] } { if { [info exists ETB_TAPID ] } {
@ -26,7 +35,10 @@ if { [info exists ETB_TAPID ] } {
} else { } else {
set _ETB_TAPID 0x2b900f0f set _ETB_TAPID 0x2b900f0f
} }
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID ] } { if { [info exists CPU_TAPID ] } {
@ -34,33 +46,34 @@ if { [info exists CPU_TAPID ] } {
} else { } else {
set _CPU_TAPID 0x07926001 set _CPU_TAPID 0x07926001
} }
jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Subsidiary TAP: C64x+ DSP ... NOT CURRENTLY INCLUDED, must add via ICEpick. # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
# Documentation for DSP JTAG interfaces evidently needs NDAs.
# Primary TAP: ICEpick (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID ] } { if { [info exists JRC_TAPID ] } {
set _JRC_TAPID $JRC_TAPID set _JRC_TAPID $JRC_TAPID
} else { } else {
set _JRC_TAPID 0x0b70002f set _JRC_TAPID 0x0b70002f
} }
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused. # and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
set _TARGETNAME $_CHIPNAME.arm set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x0000a000 -work-area-size 0x2000 -work-area-backup 0 $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
arm7_9 dbgrq enable arm7_9 dbgrq enable
arm7_9 fast_memory_access enable arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable arm7_9 dcc_downloads enable
# trace setup # trace setup
# FIXME we ought to be able to say "... config $_TARGETNAME ..." etm config $_TARGETNAME 16 normal full etb
# (not "config 0") facilitating additional targets (e.g. other chips) etb config $_TARGETNAME $_CHIPNAME.etb
etm config 0 16 normal full etb
etb config 0 $_CHIPNAME.etb
# vim:syntax tcl