From 10b08d5ac5086aed3259f4f48a67d8d807c8ef11 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 28 Sep 2022 21:38:05 +0200 Subject: [PATCH] target/xtensa: rename pc and ps macro names Actually they are the base of epc and eps Signed-off-by: Erhan Kurubas Change-Id: I4f43b9609a9929399fb5d3fa0203efc8a98e94c9 Reviewed-on: https://review.openocd.org/c/openocd/+/7227 Tested-by: jenkins Reviewed-by: Ian Thompson Reviewed-by: Antonio Borneo --- src/target/xtensa/xtensa.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index 4dfff6ab4..c73b80820 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -168,8 +168,9 @@ #define XT_REG_A3 (xtensa_regs[XT_REG_IDX_AR3].reg_num) #define XT_REG_A4 (xtensa_regs[XT_REG_IDX_AR4].reg_num) -#define XT_PS_REG_NUM_BASE (0xc0U) /* (EPS2 - 2), for adding DBGLEVEL */ -#define XT_PC_REG_NUM_BASE (0xb0U) /* (EPC1 - 1), for adding DBGLEVEL */ +#define XT_PS_REG_NUM (0xe6U) +#define XT_EPS_REG_NUM_BASE (0xc0U) /* (EPS2 - 2), for adding DBGLEVEL */ +#define XT_EPC_REG_NUM_BASE (0xb0U) /* (EPC1 - 1), for adding DBGLEVEL */ #define XT_PC_REG_NUM_VIRTUAL (0xffU) /* Marker for computing PC (EPC[DBGLEVEL) */ #define XT_PC_DBREG_NUM_BASE (0x20U) /* External (i.e., GDB) access */ @@ -245,7 +246,7 @@ struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = { XT_MK_REG_DESC("ar63", 0x3F, XT_REG_GENERAL, 0), XT_MK_REG_DESC("windowbase", 0x48, XT_REG_SPECIAL, 0), XT_MK_REG_DESC("windowstart", 0x49, XT_REG_SPECIAL, 0), - XT_MK_REG_DESC("ps", 0xE6, XT_REG_SPECIAL, 0), /* PS (not mapped through EPS[]) */ + XT_MK_REG_DESC("ps", XT_PS_REG_NUM, XT_REG_SPECIAL, 0), /* PS (not mapped through EPS[]) */ XT_MK_REG_DESC("ibreakenable", 0x60, XT_REG_SPECIAL, 0), XT_MK_REG_DESC("ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD), XT_MK_REG_DESC("ibreaka0", 0x80, XT_REG_SPECIAL, 0), @@ -630,7 +631,7 @@ static int xtensa_write_dirty_registers(struct target *target) /* reg number of PC for debug interrupt depends on NDEBUGLEVEL **/ reg_num = - (XT_PC_REG_NUM_BASE + + (XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level); xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3)); } @@ -1105,10 +1106,10 @@ int xtensa_fetch_all_regs(struct target *target) case XT_REG_SPECIAL: if (reg_num == XT_PC_REG_NUM_VIRTUAL) { /* reg number of PC for debug interrupt depends on NDEBUGLEVEL */ - reg_num = (XT_PC_REG_NUM_BASE + xtensa->core_config->debug.irq_level); + reg_num = XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level; } else if (reg_num == xtensa_regs[XT_REG_IDX_PS].reg_num) { /* reg number of PS for debug interrupt depends on NDEBUGLEVEL */ - reg_num = (XT_PS_REG_NUM_BASE + xtensa->core_config->debug.irq_level); + reg_num = XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level; } else if (reg_num == xtensa_regs[XT_REG_IDX_CPENABLE].reg_num) { /* CPENABLE already read/updated; don't re-read */ reg_fetched = false; @@ -3441,8 +3442,8 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa) else rptr->flags = 0; - if ((rptr->reg_num == (XT_PS_REG_NUM_BASE + xtensa->core_config->debug.irq_level)) && - (xtensa->core_config->core_type == XT_LX) && (rptr->type == XT_REG_SPECIAL)) { + if (rptr->reg_num == (XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level) && + xtensa->core_config->core_type == XT_LX && rptr->type == XT_REG_SPECIAL) { xtensa->eps_dbglevel_idx = XT_NUM_REGS + xtensa->num_optregs - 1; LOG_DEBUG("Setting PS (%s) index to %d", rptr->name, xtensa->eps_dbglevel_idx); }