Merge branch 'master' into from_upstream

This primarily contains the large upstreaming of RISC-V changes, so lots
more RISC-V changes than usual.

Conflicts:
	src/target/riscv/opcodes.h
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I1145dad538a5470ad209848572e6b0f560b671e9
Signed-off-by: Tim Newsome <tim@sifive.com>

src/flash/nor/psoc6.c

@@ -492,8 +492,7 @@ static const char *protection_to_str(uint8_t protection)
 /** ***********************************************************************************************
  * @brief psoc6_get_info Displays human-readable information about acquired device
  * @param bank current flash bank
- * @param buf pointer to buffer for human-readable text
+ * @param cmd pointer to command invocation instance
- * @param buf_size size of the buffer
  * @return ERROR_OK in case of success, ERROR_XXX code otherwise
  *************************************************************************************************/
 static int psoc6_get_info(struct flash_bank *bank, struct command_invocation *cmd)

src/helper/command.h

@@ -38,6 +38,15 @@
 #define PRINTF_ATTRIBUTE_FORMAT printf
 #endif
 
+/**
+ * OpenOCD command mode is COMMAND_CONFIG at start, then switches to COMMAND_EXEC
+ * during the execution of command 'init'.
+ * The field 'mode' in struct command_registration specifies in which command mode
+ * the command can be executed:
+ * - during COMMAND_CONFIG only,
+ * - during COMMAND_EXEC only,
+ * - in both modes (COMMAND_ANY).
+ */
 enum command_mode {
 	COMMAND_EXEC,
 	COMMAND_CONFIG,

src/jtag/aice/aice_interface.h

@@ -19,17 +19,6 @@
 #ifndef OPENOCD_JTAG_AICE_AICE_INTERFACE_H
 #define OPENOCD_JTAG_AICE_AICE_INTERFACE_H
 
-struct aice_interface_param_s {
-	/** */
-	const char *device_desc;
-	/** */
-	const char *serial;
-	/** */
-	uint16_t vid;
-	/** */
-	uint16_t pid;
-};
-
 int aice_init_targets(void);
 int aice_scan_jtag_chain(void);
 

src/jtag/core.c

@@ -128,7 +128,6 @@ static int speed_khz;
 /* speed to fallback to when RCLK is requested but not supported */
 static int rclk_fallback_speed_khz;
 static enum {CLOCK_MODE_UNSELECTED, CLOCK_MODE_KHZ, CLOCK_MODE_RCLK} clock_mode;
-static int jtag_speed;
 
 /* FIXME: change name to this variable, it is not anymore JTAG only */
 static struct adapter_driver *jtag;
@@ -1336,7 +1335,6 @@ static int jtag_validate_ircapture(void)
 	struct jtag_tap *tap;
 	uint8_t *ir_test = NULL;
 	struct scan_field field;
-	uint64_t val;
 	int chain_pos = 0;
 	int retval;
 
@@ -1396,7 +1394,7 @@ static int jtag_validate_ircapture(void)
 		 */
 		if (tap->ir_length == 0) {
 			tap->ir_length = 2;
-			while ((val = buf_get_u64(ir_test, chain_pos, tap->ir_length + 1)) == 1
+			while (buf_get_u64(ir_test, chain_pos, tap->ir_length + 1) == 1
 					&& tap->ir_length < JTAG_IRLEN_MAX) {
 				tap->ir_length++;
 			}
@@ -1412,7 +1410,7 @@ static int jtag_validate_ircapture(void)
 		 * this part of the JTAG spec, so their capture mask/value
 		 * attributes might disable this test.
 		 */
-		val = buf_get_u64(ir_test, chain_pos, tap->ir_length);
+		uint64_t val = buf_get_u64(ir_test, chain_pos, tap->ir_length);
 		if ((val & tap->ir_capture_mask) != tap->ir_capture_value) {
 			LOG_ERROR("%s: IR capture error; saw 0x%0*" PRIx64 " not 0x%0*" PRIx32,
 				jtag_tap_name(tap),
@@ -1428,7 +1426,7 @@ static int jtag_validate_ircapture(void)
 	}
 
 	/* verify the '11' sentinel we wrote is returned at the end */
-	val = buf_get_u64(ir_test, chain_pos, 2);
+	uint64_t val = buf_get_u64(ir_test, chain_pos, 2);
 	if (val != 0x3) {
 		char *cbuf = buf_to_hex_str(ir_test, total_ir_length);
 
@@ -1805,7 +1803,6 @@ static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int *speed)
 
 static int jtag_set_speed(int speed)
 {
-	jtag_speed = speed;
 	/* this command can be called during CONFIG,
 	 * in which case jtag isn't initialized */
 	return jtag ? jtag->speed(speed) : ERROR_OK;

src/jtag/drivers/jlink.c

@@ -39,7 +39,7 @@
 #include <jtag/swd.h>
 #include <jtag/commands.h>
 #include <jtag/drivers/jtag_usb_common.h>
-#include <src/helper/replacements.h>
+#include <helper/replacements.h>
 #include <target/cortex_m.h>
 
 #include <libjaylink/libjaylink.h>

src/jtag/hla/hla_interface.c

@@ -35,7 +35,21 @@
 
 #include <target/target.h>
 
-static struct hl_interface_s hl_if = { {0, 0, { 0 }, { 0 }, HL_TRANSPORT_UNKNOWN, false, -1, false, 7184}, 0, 0 };
+static struct hl_interface_s hl_if = {
+	.param = {
+		.device_desc = NULL,
+		.serial = NULL,
+		.vid = { 0 },
+		.pid = { 0 },
+		.transport = HL_TRANSPORT_UNKNOWN,
+		.connect_under_reset = false,
+		.initial_interface_speed = -1,
+		.use_stlink_tcp = false,
+		.stlink_tcp_port = 7184,
+	},
+	.layout = NULL,
+	.handle = NULL,
+};
 
 int hl_interface_open(enum hl_transports tr)
 {

src/target/arm_coresight.h

@@ -11,7 +11,7 @@
 #include <stdbool.h>
 #include <stdint.h>
 
-#include <src/helper/bits.h>
+#include <helper/bits.h>
 
 #define ARM_CS_ALIGN                            (0x1000)
 

src/target/arm_semihosting.c

@@ -315,7 +315,7 @@ int arm_semihosting(struct target *target, int *retval)
 				return 0;
 		} else if (arm->core_state == ARM_STATE_ARM) {
 			r = arm->pc;
-			pc = buf_get_u32(arm->pc->value, 0, 32);
+			pc = buf_get_u32(r->value, 0, 32);
 
 			/* A32 instruction => check for HLT 0xF000 (0xE10F0070) */
 			uint32_t insn = 0;
@@ -330,7 +330,7 @@ int arm_semihosting(struct target *target, int *retval)
 				return 0;
 		} else if (arm->core_state == ARM_STATE_THUMB) {
 			r = arm->pc;
-			pc = buf_get_u32(arm->pc->value, 0, 32);
+			pc = buf_get_u32(r->value, 0, 32);
 
 			/* T32 instruction => check for HLT 0x3C (0xBABC) */
 			uint16_t insn = 0;

src/target/arm_tpiu_swo.c

@@ -155,7 +155,7 @@ static int arm_tpiu_swo_poll_trace(void *priv)
 	if (obj->out_filename && obj->out_filename[0] == ':')
 		list_for_each_entry(c, &obj->connections, lh)
 			if (connection_write(c->connection, buf, size) != (int)size)
-				retval = ERROR_FAIL;
+				LOG_ERROR("Error writing to connection"); /* FIXME: which connection? */
 
 	return ERROR_OK;
 }
@@ -678,6 +678,10 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const
 
 	if (obj->pin_protocol == TPIU_SPPR_PROTOCOL_SYNC) {
 		retval = wrap_read_u32(target, tpiu_ap, obj->spot.base + TPIU_SSPSR_OFFSET, &value);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Cannot read TPIU register SSPSR");
+			return JIM_ERR;
+		}
 		if (!(value & BIT(obj->port_width - 1))) {
 			LOG_ERROR("TPIU does not support port-width of %d bits", obj->port_width);
 			return JIM_ERR;

src/target/armv8.c

@@ -454,29 +454,31 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
 		retval = dpm->instr_read_data_r0(dpm,
 				ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
 				&value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 		/* read r1 via dcc */
 		retval = dpm->instr_read_data_dcc(dpm,
 				ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
 				&value_r1);
-		if (retval == ERROR_OK) {
+		if (retval != ERROR_OK)
+			return retval;
 		*lvalue = value_r1;
 		*lvalue = ((*lvalue) << 32) | value_r0;
-		} else
-			return retval;
 
 		num++;
 		/* repeat above steps for high 64 bits of V register */
 		retval = dpm->instr_read_data_r0(dpm,
 				ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
 				&value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dpm->instr_read_data_dcc(dpm,
 				ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
 				&value_r1);
-		if (retval == ERROR_OK) {
+		if (retval != ERROR_OK)
+			return retval;
 		*hvalue = value_r1;
 		*hvalue = ((*hvalue) << 32) | value_r0;
-		} else
-			return retval;
 		break;
 	default:
 		retval = ERROR_FAIL;
@@ -586,12 +588,16 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 		retval = dpm->instr_write_data_dcc(dpm,
 			ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
 			value_r1);
+		if (retval != ERROR_OK)
+			return retval;
 		/* write value_r0 to r0 via dcc then,
 		 * move to double word register from r0:r1: "vmov vm, r0, r1"
 		 */
 		retval = dpm->instr_write_data_r0(dpm,
 			ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
 			value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		num++;
 		/* repeat above steps for high 64 bits of V register */
@@ -600,6 +606,8 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 		retval = dpm->instr_write_data_dcc(dpm,
 			ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
 			value_r1);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dpm->instr_write_data_r0(dpm,
 			ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
 			value_r0);

src/target/lakemont.c

@@ -1070,7 +1070,8 @@ int lakemont_step(struct target *t, int current,
 	LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
 			eflags, pmcr, eip);
 
-	tapstatus = get_tapstatus(t);
+	/* Returned value unused. Can this line be removed? */
+	get_tapstatus(t);
 
 	t->debug_reason = DBG_REASON_SINGLESTEP;
 	t->state = TARGET_DEBUG_RUNNING;

src/target/mips64_pracc.c

@@ -213,7 +213,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
 		      unsigned num_param_out, uint64_t *param_out)
 {
 	uint32_t ejtag_ctrl;
-	uint64_t address = 0, address_prev = 0, data;
+	uint64_t address = 0, address_prev = 0;
 	struct mips64_pracc_context ctx;
 	int retval;
 	int pass = 0;
@@ -243,7 +243,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
 			address_prev = address;
 		else
 			address_prev = 0;
-		address32 = data = 0;
+		address32 = 0;
 
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 		mips_ejtag_drscan_32(ejtag_info, &address32);
@@ -1358,8 +1358,6 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 			  0, NULL, 0, NULL);
 
 	/* next fetch to dmseg should be in FASTDATA_AREA, check */
-	address = 0;
-
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	retval = mips_ejtag_drscan_32(ejtag_info, &address32);
 	if (retval != ERROR_OK)
@@ -1411,7 +1409,6 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 		return retval;
 	}
 
-	address = 0;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	retval = mips_ejtag_drscan_32(ejtag_info, &address32);
 	if (retval != ERROR_OK) {

src/target/riscv/batch.c

@@ -27,23 +27,33 @@ struct riscv_batch *riscv_batch_alloc(struct target *target, size_t scans, size_
 	out->allocated_scans = scans;
 	out->idle_count = idle;
 	out->data_out = malloc(sizeof(*out->data_out) * (scans) * DMI_SCAN_BUF_SIZE);
-	if (!out->data_out)
+	if (!out->data_out) {
+		LOG_ERROR("Failed to allocate data_out in RISC-V batch.");
 		goto error1;
+	};
 	out->data_in = malloc(sizeof(*out->data_in) * (scans) * DMI_SCAN_BUF_SIZE);
-	if (!out->data_in)
+	if (!out->data_in) {
+		LOG_ERROR("Failed to allocate data_in in RISC-V batch.");
 		goto error2;
+	}
 	out->fields = malloc(sizeof(*out->fields) * (scans));
-	if (!out->fields)
+	if (!out->fields) {
+		LOG_ERROR("Failed to allocate fields in RISC-V batch.");
 		goto error3;
+	}
 	if (bscan_tunnel_ir_width != 0) {
 		out->bscan_ctxt = malloc(sizeof(*out->bscan_ctxt) * (scans));
-		if (!out->bscan_ctxt)
+		if (!out->bscan_ctxt) {
+			LOG_ERROR("Failed to allocate bscan_ctxt in RISC-V batch.");
 			goto error4;
 		}
+	}
 	out->last_scan = RISCV_SCAN_TYPE_INVALID;
 	out->read_keys = malloc(sizeof(*out->read_keys) * (scans));
-	if (!out->read_keys)
+	if (!out->read_keys) {
+		LOG_ERROR("Failed to allocate read_keys in RISC-V batch.");
 		goto error5;
+	}
 	return out;
 
 error5:

src/target/riscv/riscv-011.c

@@ -2336,7 +2336,7 @@ static int wait_for_authbusy(struct target *target)
 	return ERROR_OK;
 }
 
-static int riscv011_authdata_read(struct target *target, uint32_t *value, unsigned index)
+static int riscv011_authdata_read(struct target *target, uint32_t *value, unsigned int index)
 {
 	if (index > 1) {
 		LOG_ERROR("Spec 0.11 only has a two authdata registers.");
@@ -2352,7 +2352,7 @@ static int riscv011_authdata_read(struct target *target, uint32_t *value, unsign
 	return ERROR_OK;
 }
 
-static int riscv011_authdata_write(struct target *target, uint32_t value, unsigned index)
+static int riscv011_authdata_write(struct target *target, uint32_t value, unsigned int index)
 {
 	if (index > 1) {
 		LOG_ERROR("Spec 0.11 only has a two authdata registers.");

src/target/riscv/riscv-013.c

@@ -1768,7 +1768,7 @@ static int examine(struct target *target)
 	return ERROR_OK;
 }
 
-static int riscv013_authdata_read(struct target *target, uint32_t *value, unsigned index)
+static int riscv013_authdata_read(struct target *target, uint32_t *value, unsigned int index)
 {
 	if (index > 0) {
 		LOG_ERROR("Spec 0.13 only has a single authdata register.");
@@ -1781,7 +1781,7 @@ static int riscv013_authdata_read(struct target *target, uint32_t *value, unsign
 	return dmi_read(target, value, DM_AUTHDATA);
 }
 
-static int riscv013_authdata_write(struct target *target, uint32_t value, unsigned index)
+static int riscv013_authdata_write(struct target *target, uint32_t value, unsigned int index)
 {
 	if (index > 0) {
 		LOG_ERROR("Spec 0.13 only has a single authdata register.");
@@ -1828,7 +1828,7 @@ static unsigned riscv013_data_bits(struct target *target)
 	RISCV013_INFO(info);
 	RISCV_INFO(r);
 
-	for (unsigned i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
+	for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
 		int method = r->mem_access_methods[i];
 
 		if (method == RISCV_MEM_ACCESS_PROGBUF) {
@@ -2038,7 +2038,7 @@ static int riscv013_set_register_buf(struct target *target,
 	return result;
 }
 
-static uint32_t sb_sbaccess(unsigned size_bytes)
+static uint32_t sb_sbaccess(unsigned int size_bytes)
 {
 	switch (size_bytes) {
 		case 1:
@@ -2053,14 +2053,14 @@ static uint32_t sb_sbaccess(unsigned size_bytes)
 			return set_field(0, DM_SBCS_SBACCESS, 4);
 	}
 	assert(0);
-	return 0;	/* Make mingw happy. */
+	return 0;
 }
 
 static int sb_write_address(struct target *target, target_addr_t address,
 							bool ensure_success)
 {
 	RISCV013_INFO(info);
-	unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
+	unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
 	/* There currently is no support for >64-bit addresses in OpenOCD. */
 	if (sbasize > 96)
 		dmi_op(target, NULL, NULL, DMI_OP_WRITE, DM_SBADDRESS3, 0, false, false);
@@ -2087,7 +2087,7 @@ static int batch_run(const struct target *target, struct riscv_batch *batch)
 	return riscv_batch_run(batch);
 }
 
-static int sba_supports_access(struct target *target, unsigned size_bytes)
+static int sba_supports_access(struct target *target, unsigned int size_bytes)
 {
 	RISCV013_INFO(info);
 	switch (size_bytes) {
@@ -2107,12 +2107,12 @@ static int sba_supports_access(struct target *target, unsigned size_bytes)
 }
 
 static int sample_memory_bus_v1(struct target *target,
-								riscv_sample_buf_t *buf,
+								struct riscv_sample_buf *buf,
 								const riscv_sample_config_t *config,
 								int64_t until_ms)
 {
 	RISCV013_INFO(info);
-	unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
+	unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
 	if (sbasize > 64) {
 		LOG_ERROR("Memory sampling is only implemented for sbasize <= 64.");
 		return ERROR_NOT_IMPLEMENTED;
@@ -2132,10 +2132,10 @@ static int sample_memory_bus_v1(struct target *target,
 	bool sbaddress1_valid = false;
 
 	/* How often to read each value in a batch. */
-	const unsigned repeat = 5;
+	const unsigned int repeat = 5;
 
-	unsigned enabled_count = 0;
+	unsigned int enabled_count = 0;
-	for (unsigned i = 0; i < ARRAY_SIZE(config->bucket); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
 		if (config->bucket[i].enabled)
 			enabled_count++;
 	}
@@ -2149,10 +2149,12 @@ static int sample_memory_bus_v1(struct target *target,
 		struct riscv_batch *batch = riscv_batch_alloc(
 			target, 1 + enabled_count * 5 * repeat,
 			info->dmi_busy_delay + info->bus_master_read_delay);
+		if (!batch)
+			return ERROR_FAIL;
 
-		unsigned result_bytes = 0;
+		unsigned int result_bytes = 0;
-		for (unsigned n = 0; n < repeat; n++) {
+		for (unsigned int n = 0; n < repeat; n++) {
-			for (unsigned i = 0; i < ARRAY_SIZE(config->bucket); i++) {
+			for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
 				if (config->bucket[i].enabled) {
 					if (!sba_supports_access(target, config->bucket[i].size_bytes)) {
 						LOG_ERROR("Hardware does not support SBA access for %d-byte memory sampling.",
@@ -2218,9 +2220,9 @@ static int sample_memory_bus_v1(struct target *target,
 			return ERROR_FAIL;
 		}
 
-		unsigned read = 0;
+		unsigned int read = 0;
-		for (unsigned n = 0; n < repeat; n++) {
+		for (unsigned int n = 0; n < repeat; n++) {
-			for (unsigned i = 0; i < ARRAY_SIZE(config->bucket); i++) {
+			for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
 				if (config->bucket[i].enabled) {
 					assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
 					uint64_t value = 0;
@@ -2242,7 +2244,7 @@ static int sample_memory_bus_v1(struct target *target,
 }
 
 static int sample_memory(struct target *target,
-						 riscv_sample_buf_t *buf,
+						 struct riscv_sample_buf *buf,
 						 riscv_sample_config_t *config,
 						 int64_t until_ms)
 {
@@ -2876,7 +2878,7 @@ static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
 		*skip_reason = "skipped (unsupported size)";
 		return true;
 	}
-	unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
+	unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
 	if ((sizeof(address) * 8 > sbasize) && (address >> sbasize)) {
 		LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.",
 				read ? "read" : "write", sbasize);
@@ -2949,7 +2951,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
 	/* Execute the reads */
 	uint8_t *p = buffer;
 	bool updateaddr = true;
-	unsigned width32 = (width < 32) ? 32 : width;
+	unsigned int width32 = (width < 32) ? 32 : width;
 	for (uint32_t c = 0; c < count; c++) {
 		/* Update the address if it is the first time or aampostincrement is not supported by the target. */
 		if (updateaddr) {
@@ -3519,7 +3521,7 @@ static int read_memory(struct target *target, target_addr_t address,
 	char *sysbus_result = "disabled";
 	char *abstract_result = "disabled";
 
-	for (unsigned i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
+	for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
 		int method = r->mem_access_methods[i];
 
 		if (method == RISCV_MEM_ACCESS_PROGBUF) {
@@ -3732,7 +3734,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
 			continue;
 		}
 
-		unsigned sberror = get_field(sbcs, DM_SBCS_SBERROR);
+		unsigned int sberror = get_field(sbcs, DM_SBCS_SBERROR);
 		if (sberror != 0) {
 			/* Sberror indicates the bus access failed, but not because we issued the writes
 			 * too fast. Cannot recover. Sbaddress holds the address where the error occurred
@@ -3959,7 +3961,7 @@ static int write_memory(struct target *target, target_addr_t address,
 	char *sysbus_result = "disabled";
 	char *abstract_result = "disabled";
 
-	for (unsigned i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
+	for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++) {
 		int method = r->mem_access_methods[i];
 
 		if (method == RISCV_MEM_ACCESS_PROGBUF) {
@@ -4284,7 +4286,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
 	if (result != ERROR_OK)
 		return RISCV_HALT_UNKNOWN;
 
-	LOG_DEBUG("dcsr.cause: 0x%x", (unsigned int)get_field(dcsr, CSR_DCSR_CAUSE));
+	LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
 
 	switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
 	case CSR_DCSR_CAUSE_SWBP:
@@ -4305,8 +4307,8 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
 		return RISCV_HALT_GROUP;
 	}
 
-	LOG_ERROR("Unknown DCSR cause field: 0x%x", (unsigned int)get_field(dcsr, CSR_DCSR_CAUSE));
+	LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
-	LOG_ERROR("  dcsr=0x%016lx", (long)dcsr);
+	LOG_ERROR("  dcsr=0x%" PRIx32, (uint32_t) dcsr);
 	return RISCV_HALT_UNKNOWN;
 }
 

src/target/riscv/riscv.c

@@ -22,6 +22,7 @@
 #include "gdb_regs.h"
 #include "rtos/rtos.h"
 #include "debug_defines.h"
+#include <helper/bits.h>
 
 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
@@ -428,8 +429,10 @@ static int riscv_create_target(struct target *target, Jim_Interp *interp)
 {
 	LOG_DEBUG("riscv_create_target()");
 	target->arch_info = calloc(1, sizeof(riscv_info_t));
-	if (!target->arch_info)
+	if (!target->arch_info) {
+		LOG_ERROR("Failed to allocate RISC-V target structure.");
 		return ERROR_FAIL;
+	}
 	riscv_info_init(target, target->arch_info);
 	return ERROR_OK;
 }
@@ -486,7 +489,7 @@ static void riscv_deinit_target(struct target *target)
 {
 	LOG_DEBUG("riscv_deinit_target()");
 
-	riscv_info_t *info = (riscv_info_t *) target->arch_info;
+	riscv_info_t *info = target->arch_info;
 	struct target_type *tt = get_target_type(target);
 
 	if (tt && info->version_specific)
@@ -548,11 +551,11 @@ static int maybe_add_trigger_t1(struct target *target,
 	tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 	tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 	tdata1 = set_field(tdata1, bpcontrol_u,
-			!!(r->misa & (1 << ('U' - 'A'))));
+			!!(r->misa & BIT('U' - 'A')));
 	tdata1 = set_field(tdata1, bpcontrol_s,
-			!!(r->misa & (1 << ('S' - 'A'))));
+			!!(r->misa & BIT('S' - 'A')));
 	tdata1 = set_field(tdata1, bpcontrol_h,
-			!!(r->misa & (1 << ('H' - 'A'))));
+			!!(r->misa & BIT('H' - 'A')));
 	tdata1 |= bpcontrol_m;
 	tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 	tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
@@ -752,8 +755,8 @@ static int write_by_given_size(struct target *target, target_addr_t address,
 		/* Can do the memory access directly without a helper buffer. */
 		return target_write_memory(target, address, access_size, size / access_size, buffer);
 
-	unsigned offset_head = address % access_size;
+	unsigned int offset_head = address % access_size;
-	unsigned n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
+	unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 	uint8_t helper_buf[n_blocks * access_size];
 
 	/* Read from memory */
@@ -779,8 +782,8 @@ static int read_by_given_size(struct target *target, target_addr_t address,
 		/* Can do the memory access directly without a helper buffer. */
 		return target_read_memory(target, address, access_size, size / access_size, buffer);
 
-	unsigned offset_head = address % access_size;
+	unsigned int offset_head = address % access_size;
-	unsigned n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
+	unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 	uint8_t helper_buf[n_blocks * access_size];
 
 	/* Read from memory */
@@ -801,7 +804,7 @@ int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32
 	assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 
 	/* Find access size that correspond to data size and the alignment. */
-	unsigned preferred_size = size;
+	unsigned int preferred_size = size;
 	while (address % preferred_size != 0)
 		preferred_size /= 2;
 
@@ -811,7 +814,7 @@ int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32
 
 	/* On failure, try other access sizes.
 	   Minimize the number of accesses by trying first the largest size. */
-	for (unsigned access_size = 8; access_size > 0; access_size /= 2) {
+	for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 		if (access_size == preferred_size)
 			/* Already tried this size. */
 			continue;
@@ -833,7 +836,7 @@ int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_
 	assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 
 	/* Find access size that correspond to data size and the alignment. */
-	unsigned preferred_size = size;
+	unsigned int preferred_size = size;
 	while (address % preferred_size != 0)
 		preferred_size /= 2;
 
@@ -843,7 +846,7 @@ int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_
 
 	/* On failure, try other access sizes.
 	   Minimize the number of accesses by trying first the largest size. */
-	for (unsigned access_size = 8; access_size > 0; access_size /= 2) {
+	for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 		if (access_size == preferred_size)
 			/* Already tried this size. */
 			continue;
@@ -1315,7 +1318,7 @@ static int disable_triggers(struct target *target, riscv_reg_t *state)
 		riscv_reg_t tselect;
 		if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
 			return ERROR_FAIL;
-		for (unsigned t = 0; t < r->trigger_count; t++) {
+		for (unsigned int t = 0; t < r->trigger_count; t++) {
 			if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
 				return ERROR_FAIL;
 			riscv_reg_t tdata1;
@@ -1358,7 +1361,7 @@ static int enable_triggers(struct target *target, riscv_reg_t *state)
 		riscv_reg_t tselect;
 		if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
 			return ERROR_FAIL;
-		for (unsigned t = 0; t < r->trigger_count; t++) {
+		for (unsigned int t = 0; t < r->trigger_count; t++) {
 			if (state[t] != 0) {
 				if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
 					return ERROR_FAIL;
@@ -1990,10 +1993,10 @@ static int riscv_checksum_memory(struct target *target,
 	LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
 
 	static const uint8_t riscv32_crc_code[] = {
-#include "contrib/loaders/checksum/riscv32_crc.inc"
+#include "../../../contrib/loaders/checksum/riscv32_crc.inc"
 	};
 	static const uint8_t riscv64_crc_code[] = {
-#include "contrib/loaders/checksum/riscv64_crc.inc"
+#include "../../../contrib/loaders/checksum/riscv64_crc.inc"
 	};
 
 	static const uint8_t *crc_code;
@@ -2146,7 +2149,7 @@ int sample_memory(struct target *target)
 
 	/* Default slow path. */
 	while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
-		for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
+		for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
 			if (r->sample_config.bucket[i].enabled &&
 					r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
 				assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
@@ -2246,7 +2249,7 @@ int riscv_openocd_poll(struct target *target)
 		}
 
 		/* Sample memory if any target is running. */
-		for (struct target_list *list = target->head; list != NULL;
+		for (struct target_list *list = target->head; list;
 				list = list->next, i++) {
 			struct target *t = list->target;
 			if (t->state == TARGET_RUNNING) {
@@ -2264,9 +2267,9 @@ int riscv_openocd_poll(struct target *target)
 			if (target->state == TARGET_RUNNING)
 				sample_memory(target);
 			return ERROR_OK;
-		}
+		} else if (out == RPH_ERROR) {
-		else if (out == RPH_ERROR)
 			return ERROR_FAIL;
+		}
 
 		halted_hart = riscv_current_hartid(target);
 		LOG_DEBUG("  hart %d halted", halted_hart);
@@ -2408,14 +2411,14 @@ COMMAND_HANDLER(riscv_set_mem_access)
 	}
 
 	/* Check argument validity */
-	for (unsigned i = 0; i < CMD_ARGC; i++) {
+	for (unsigned int i = 0; i < CMD_ARGC; i++) {
-		if (strcmp("progbuf", CMD_ARGV[i]) == 0)
+		if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
 			progbuf_cnt++;
-		else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
+		} else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
 			sysbus_cnt++;
-		else if (strcmp("abstract", CMD_ARGV[i]) == 0)
+		} else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
 			abstract_cnt++;
-		else {
+		} else {
 			LOG_ERROR("Unknown argument '%s'. "
 				"Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
 			return ERROR_COMMAND_SYNTAX_ERROR;
@@ -2427,9 +2430,9 @@ COMMAND_HANDLER(riscv_set_mem_access)
 	}
 
 	/* Args are valid, store them */
-	for (unsigned i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
+	for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
 		r->mem_access_methods[i] = RISCV_MEM_ACCESS_UNSPECIFIED;
-	for (unsigned i = 0; i < CMD_ARGC; i++) {
+	for (unsigned int i = 0; i < CMD_ARGC; i++) {
 		if (strcmp("progbuf", CMD_ARGV[i]) == 0)
 			r->mem_access_methods[i] = RISCV_MEM_ACCESS_PROGBUF;
 		else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
@@ -2456,7 +2459,7 @@ COMMAND_HANDLER(riscv_set_enable_virtual)
 	return ERROR_OK;
 }
 
-int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned max_val)
+int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
 {
 	char *args = strdup(tcl_arg);
 	if (!args)
@@ -2471,7 +2474,7 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
 
 		char *dash = strchr(arg, '-');
 		char *equals = strchr(arg, '=');
-		unsigned pos;
+		unsigned int pos;
 
 		if (!dash && !equals) {
 			/* Expecting single register number. */
@@ -2511,6 +2514,7 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
 
 			name = calloc(1, strlen(equals) + strlen(reg_type) + 2);
 			if (!name) {
+				LOG_ERROR("Failed to allocate register name.");
 				free(args);
 				return ERROR_FAIL;
 			}
@@ -2562,6 +2566,7 @@ int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_
 
 		range_list_t *range = calloc(1, sizeof(range_list_t));
 		if (!range) {
+			LOG_ERROR("Failed to allocate range list.");
 			free(name);
 			free(args);
 			return ERROR_FAIL;
@@ -2590,7 +2595,7 @@ COMMAND_HANDLER(riscv_set_expose_csrs)
 	RISCV_INFO(info);
 	int ret = ERROR_OK;
 
-	for (unsigned i = 0; i < CMD_ARGC; i++) {
+	for (unsigned int i = 0; i < CMD_ARGC; i++) {
 		ret = parse_ranges(&info->expose_csr, CMD_ARGV[i], "csr", 0xfff);
 		if (ret != ERROR_OK)
 			break;
@@ -2610,7 +2615,7 @@ COMMAND_HANDLER(riscv_set_expose_custom)
 	RISCV_INFO(info);
 	int ret = ERROR_OK;
 
-	for (unsigned i = 0; i < CMD_ARGC; i++) {
+	for (unsigned int i = 0; i < CMD_ARGC; i++) {
 		ret = parse_ranges(&info->expose_custom, CMD_ARGV[i], "custom", 0x3fff);
 		if (ret != ERROR_OK)
 			break;
@@ -2621,7 +2626,7 @@ COMMAND_HANDLER(riscv_set_expose_custom)
 
 COMMAND_HANDLER(riscv_authdata_read)
 {
-	unsigned index = 0;
+	unsigned int index = 0;
 	if (CMD_ARGC == 0) {
 		/* nop */
 	} else if (CMD_ARGC == 1) {
@@ -2658,7 +2663,7 @@ COMMAND_HANDLER(riscv_authdata_read)
 COMMAND_HANDLER(riscv_authdata_write)
 {
 	uint32_t value;
-	unsigned index = 0;
+	unsigned int index = 0;
 
 	if (CMD_ARGC == 0) {
 		/* nop */
@@ -3100,21 +3105,21 @@ static const struct command_registration riscv_exec_command_handlers[] = {
 		.name = "dump_sample_buf",
 		.handler = handle_dump_sample_buf_command,
 		.mode = COMMAND_ANY,
-		.usage = "riscv dump_sample_buf [base64]",
+		.usage = "[base64]",
 		.help = "Print the contents of the sample buffer, and clear the buffer."
 	},
 	{
 		.name = "info",
 		.handler = handle_info,
 		.mode = COMMAND_ANY,
-		.usage = "riscv info",
+		.usage = "",
 		.help = "Displays some information OpenOCD detected about the target."
 	},
 	{
 		.name = "memory_sample",
 		.handler = handle_memory_sample_command,
 		.mode = COMMAND_ANY,
-		.usage = "riscv memory_sample bucket address|clear [size=4]",
+		.usage = "bucket address|clear [size=4]",
 		.help = "Causes OpenOCD to frequently read size bytes at the given address."
 	},
 	{
@@ -3468,7 +3473,7 @@ bool riscv_supports_extension(struct target *target, char letter)
 		num = letter - 'A';
 	else
 		return false;
-	return r->misa & (1 << num);
+	return r->misa & BIT(num);
 }
 
 unsigned riscv_xlen(const struct target *target)
@@ -3609,6 +3614,8 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
 {
 	RISCV_INFO(r);
 
+	keep_alive();
+
 	struct reg *reg = &target->reg_cache->reg_list[regid];
 	if (!reg->exist) {
 		LOG_DEBUG("[%s] %s does not exist.",
@@ -3762,7 +3769,7 @@ int riscv_enumerate_triggers(struct target *target)
 		return ERROR_OK;
 	}
 
-	for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
+	for (unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
 		r->trigger_count = t;
 
 		/* If we can't write tselect, then this hart does not support triggers. */

src/target/riscv/riscv.h

@@ -63,11 +63,11 @@ typedef struct {
 
 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE	0x80
 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER	0x81
-typedef struct {
+struct riscv_sample_buf {
 	uint8_t *buf;
-	unsigned used;
+	unsigned int used;
-	unsigned size;
+	unsigned int size;
-} riscv_sample_buf_t;
+};
 
 typedef struct {
 	bool enabled;
@@ -109,10 +109,10 @@ typedef struct {
 	int xlen;
 	riscv_reg_t misa;
 	/* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
-	unsigned vlenb;
+	unsigned int vlenb;
 
 	/* The number of triggers per hart. */
-	unsigned trigger_count;
+	unsigned int trigger_count;
 
 	/* For each physical trigger, contains -1 if the hwbp is available, or the
 	 * unique_id of the breakpoint/watchpoint that is using it.
@@ -171,8 +171,8 @@ typedef struct {
 	void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
 	void (*fill_dmi_nop_u64)(struct target *target, char *buf);
 
-	int (*authdata_read)(struct target *target, uint32_t *value, unsigned index);
+	int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
-	int (*authdata_write)(struct target *target, uint32_t value, unsigned index);
+	int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
 
 	int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
 	int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
@@ -181,7 +181,7 @@ typedef struct {
 			uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
 
 	int (*sample_memory)(struct target *target,
-						 riscv_sample_buf_t *buf,
+						 struct riscv_sample_buf *buf,
 						 riscv_sample_config_t *config,
 						 int64_t until_ms);
 
@@ -231,11 +231,11 @@ typedef struct {
 	struct list_head expose_custom;
 
 	riscv_sample_config_t sample_config;
-	riscv_sample_buf_t sample_buf;
+	struct riscv_sample_buf sample_buf;
 } riscv_info_t;
 
 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
-			   unsigned value);
+			   unsigned int value);
 
 typedef struct {
 	uint8_t tunneled_dr_width;

tcl/target/stm32mp15x.cfg

@@ -97,6 +97,9 @@ axi_secure
 proc dbgmcu_enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+	# freeze watchdog 1 and 2 on cores halted
+	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
 proc toggle_cpu0_dbg_claim0 {} {
@@ -116,7 +119,7 @@ proc rcc_enable_traceclk {} {
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
 $_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}