arm920t: add mrcmcr interface fn's.
The arm920t has a concept of read modify write cycles that may have to be represented in the mrcmcr interface eventually. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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@ -46,6 +46,10 @@ int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
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#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
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static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
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static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
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target_type_t arm920t_target =
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{
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.name = "arm920t",
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@ -84,6 +88,8 @@ target_type_t arm920t_target =
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.target_create = arm920t_target_create,
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.init_target = arm920t_init_target,
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.examine = arm9tdmi_examine,
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.mrc = arm920t_mrc,
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.mcr = arm920t_mcr,
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};
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int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
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@ -1407,3 +1413,26 @@ int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *c
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return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
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}
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static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
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{
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if (cpnum!=15)
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{
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
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}
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static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
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{
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if (cpnum!=15)
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{
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
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}
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