interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Kees Jongenburger <kees.jongenburger@gmail.com> - now compiles 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1201 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-12-02 07:22:53 +00:00
parent 23aa223ec4
commit 0c160046d7
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
contrib/libdcc/dcc_stdio.c
View File

@ -24,6 +24,11 @@
#include "dcc_stdio.h"
#define TARGET_REQ_TRACEMSG 0x00
#define TARGET_REQ_DEBUGMSG_ASCII 0x01
#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
#define TARGET_REQ_DEBUGCHAR 0x02
#if defined(__ARM_ARCH_7M__)
/* we use the cortex_m3 DCRDR reg to simulate a arm7_9 dcc channel
@ -34,11 +39,6 @@
#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
#define TARGET_REQ_TRACEMSG 0x00
#define TARGET_REQ_DEBUGMSG_ASCII 0x01
#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
#define TARGET_REQ_DEBUGCHAR 0x02
#define BUSY 1
void dbg_write(unsigned long dcc_data)
@ -56,7 +56,7 @@ void dbg_write(unsigned long dcc_data)
}
}
#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__)
#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__)
void dbg_write(unsigned long dcc_data)
{