Fix m*deleg logic.

Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00 · 2018-03-26 16:00:34 -07:00 · 0c05aafbf8
parent b6dca68b2e
commit 0c05aafbf8
1 changed files with 1 additions and 2 deletions
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@ -2328,8 +2328,7 @@ int riscv_init_registers(struct target *target)
 					/* "In systems with only M-mode, or with both M-mode and
 					 * U-mode but without U-mode trap support, the medeleg and
 					 * mideleg registers should not exist." */
-					r->exist = (riscv_supports_extension(target, 'S') ||
-							riscv_supports_extension(target, 'U')) &&
+					r->exist = riscv_supports_extension(target, 'S') ||
 						!riscv_supports_extension(target, 'N');
 					break;
 			}