Merge pull request #1210 from en-sc/en-sc/from_upstream

Merge up to 26f2df80c3 from upstream
2025-01-27 14:04:18 +03:00 · 2025-01-27 14:04:18 +03:00 · 058891a62a
parent dd69b78fed 182092a364
commit 058891a62a
53 changed files with 678 additions and 421 deletions
--- a/config_subdir.m4
+++ b/config_subdir.m4
@ -7,6 +7,6 @@ AC_DEFUN([AX_CONFIG_SUBDIR_OPTION],
 AC_CONFIG_SUBDIRS([$1])

 m4_ifblank([$2], [rm -f $srcdir/$1/configure.gnu],
-[echo -e '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" '"$2"' "'\$'@"' > "$srcdir/$1/configure.gnu"
+[printf '#!/bin/sh\nexec "`dirname "'\$'0"`/configure" '"$2"' "'\$'@"\n' > "$srcdir/$1/configure.gnu"
 ])
 ])
--- a/configure.ac
+++ b/configure.ac
@ -291,12 +291,11 @@ AC_ARG_ADAPTERS([
  LIBFTDI_USB1_ADAPTERS,
  LIBGPIOD_ADAPTERS,
  SERIAL_PORT_ADAPTERS,
+  DUMMY_ADAPTER,
  PCIE_ADAPTERS,
  LIBJAYLINK_ADAPTERS
  ],[auto])

-AC_ARG_ADAPTERS([DUMMY_ADAPTER],[no])
-
 AC_ARG_ENABLE([parport],
  AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
  [build_parport=$enableval], [build_parport=no])
@ -417,8 +416,8 @@ AS_CASE(["${host_cpu}"],

 can_build_buspirate=yes

-AS_CASE([$host],
-  [*-cygwin*], [
+AS_CASE([$host_os],
+  [cygwin*], [
    is_win32=yes
    parport_use_ppdev=no

@ -438,7 +437,7 @@ AS_CASE([$host],
      ])
    ])
  ],
-  [*-mingw* | *-msys*], [
+  [mingw* | msys*], [
    is_mingw=yes
    is_win32=yes
    parport_use_ppdev=no
@ -457,7 +456,7 @@ AS_CASE([$host],

    AC_SUBST([HOST_CPPFLAGS], ["-D__USE_MINGW_ANSI_STDIO -DFD_SETSIZE=128"])
  ],
-  [*darwin*], [
+  [darwin*], [
    is_darwin=yes

    AS_IF([test "x$parport_use_giveio" = "xyes"], [
@ -515,7 +514,7 @@ AS_IF([test "x$build_dmem" = "xyes"], [
  AC_DEFINE([BUILD_DMEM], [0], [0 if you don't want to debug via Direct Mem.])
 ])

-AS_IF([test "x$ADAPTER_VAR([dummy])" = "xyes"], [
+AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
  build_bitbang=yes
 ])

--- a/contrib/list_example.c
+++ b/contrib/list_example.c
@ -12,7 +12,7 @@
 #include <assert.h>
 #include <helper/list.h>

-static LIST_HEAD(threads);
+static OOCD_LIST_HEAD(threads);

 struct thread {
 	int id;
--- a/doc/manual/style.txt
+++ b/doc/manual/style.txt
@ -225,6 +225,21 @@ if (!buf) {
 }
@endcode

+@section stylelogging Logging
+
+Logging is intended to provide human-readable information to users.
+Do not confuse logging with the output of commands.
+The latter is intended for the result of a command and should be able to be processed by Tcl scripts.
+
+ - Use one of the following functions to generate log messages, never use `printf()` or similar functions.
+   - Use `LOG_ERROR()` to provide information in case an operation failed in an unrecoverable way. For example, if necessary memory cannot be allocated.
+   - Use `LOG_WARNING()` to inform the user of about an unexpected behavior that can be handled and the intended operation is still be performed. For example, in case a command is deprecated but is nevertheless executed.
+   - Use `LOG_INFO()` to provide insightful or necessary information to the user. For example, features or capabilities of a discovered target.
+   - Use `LOG_DEBUG()` to provide information for troubleshooting. For example, detailed information which makes it easier to debug a specific operation. Try to avoid flooding the log with frequently generated messages. For example, do not use LOG_DEBUG() in operations used for polling the target. Use LOG_DEBUG_IO() for such frequent messages.
+   - Use `LOG_DEBUG_IO()` to provide I/O related information for troubleshooting. For example, details about the communication between OpenOCD and a debug adapter.
+ - If the log message is related to a target, use the corresponding `LOG_TARGET_xxx()` functions.
+ - Do not use a period or exclamation mark at the end of a message.
+
 */
 /** @page styledoxygen Doxygen Style Guide

--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@ -8030,7 +8030,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn

@deffn {Flash Driver} {stm32l4x}
-All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
+All members of the STM32 C0, G0, G4, L4, L4+, L5, U0, U5, WB and WL
 microcontroller families from STMicroelectronics include internal flash
 and use ARM Cortex-M0+, M4 and M33 cores.
 The driver automatically recognizes a number of these chips using
--- a/src/flash/nor/sfdp.c
+++ b/src/flash/nor/sfdp.c
@ -103,7 +103,7 @@ int spi_sfdp(struct flash_bank *bank, struct flash_device *dev,
 		uint16_t id = (((pheaders[k].ptr) >> 16) & 0xFF00) | (pheaders[k].revision & 0xFF);
 		uint32_t ptr = pheaders[k].ptr & 0xFFFFFF;

-		LOG_DEBUG("pheader %d len=0x%02" PRIx8 " id=0x%04" PRIx16
+		LOG_DEBUG("pheader %d len=0x%02x id=0x%04" PRIx16
 			" ptr=0x%06" PRIx32, k, words, id, ptr);

 		/* retrieve parameter table */
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@ -120,6 +120,12 @@
 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
 */

+/* STM32U0xxx series for reference.
+ *
+ * RM0503 (STM32U0xx)
+ * https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+ */
+
 /* STM32U5xxx series for reference.
 *
 * RM0456 (STM32U5xx)
@ -278,7 +284,7 @@ struct stm32l4_wrp {
 };

 /* human readable list of families this drivers supports (sorted alphabetically) */
-static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
+static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U5/WB/WL";

 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
 	{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
@ -297,6 +303,10 @@ static const struct stm32l4_rev stm32c03xx_revs[] = {
 	{ 0x1000, "A" }, { 0x1001, "Z" },
 };

+static const struct stm32l4_rev stm32c071xx_revs[] = {
+	{ 0x1001, "Z" },
+};
+
 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
 	{ 0x1000, "A" },
 };
@ -325,6 +335,10 @@ static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
 	{ 0x1000, "A" },
 };

+static const struct stm32l4_rev stm32u0xx_revs[] = {
+	{ 0x1000, "A" },
+};
+
 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
 	{ 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
 };
@ -432,6 +446,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .otp_base              = 0x1FFF7000,
 	  .otp_size              = 1024,
 	},
+	{
+	  .id                    = DEVID_STM32C071XX,
+	  .revs                  = stm32c071xx_revs,
+	  .num_revs              = ARRAY_SIZE(stm32c071xx_revs),
+	  .device_str            = "STM32C071xx",
+	  .max_flash_size_kb     = 128,
+	  .flags                 = F_NONE,
+	  .flash_regs_base       = 0x40022000,
+	  .fsize_addr            = 0x1FFF75A0,
+	  .otp_base              = 0x1FFF7000,
+	  .otp_size              = 1024,
+	},
 	{
 	  .id                    = DEVID_STM32U53_U54XX,
 	  .revs                  = stm32u53_u54xx_revs,
@ -600,6 +626,30 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .otp_base              = 0x1FFF7000,
 	  .otp_size              = 1024,
 	},
+	{
+	  .id                    = DEVID_STM32U031XX,
+	  .revs                  = stm32u0xx_revs,
+	  .num_revs              = ARRAY_SIZE(stm32u0xx_revs),
+	  .device_str            = "STM32U031xx",
+	  .max_flash_size_kb     = 64,
+	  .flags                 = F_NONE,
+	  .flash_regs_base       = 0x40022000,
+	  .fsize_addr            = 0x1FFF3EA0,
+	  .otp_base              = 0x1FFF6800,
+	  .otp_size              = 1024,
+	},
+	{
+	  .id                    = DEVID_STM32U073_U083XX,
+	  .revs                  = stm32u0xx_revs,
+	  .num_revs              = ARRAY_SIZE(stm32u0xx_revs),
+	  .device_str            = "STM32U073/U083xx",
+	  .max_flash_size_kb     = 256,
+	  .flags                 = F_NONE,
+	  .flash_regs_base       = 0x40022000,
+	  .fsize_addr            = 0x1FFF6EA0,
+	  .otp_base              = 0x1FFF6800,
+	  .otp_size              = 1024,
+	},
 	{
 	  .id                    = DEVID_STM32U59_U5AXX,
 	  .revs                  = stm32u59_u5axx_revs,
@ -1955,8 +2005,11 @@ static int stm32l4_probe(struct flash_bank *bank)
 	case DEVID_STM32L43_L44XX:
 	case DEVID_STM32C01XX:
 	case DEVID_STM32C03XX:
+	case DEVID_STM32C071XX:
 	case DEVID_STM32G05_G06XX:
 	case DEVID_STM32G07_G08XX:
+	case DEVID_STM32U031XX:
+	case DEVID_STM32U073_U083XX:
 	case DEVID_STM32L45_L46XX:
 	case DEVID_STM32L41_L42XX:
 	case DEVID_STM32G03_G04XX:
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@ -91,6 +91,7 @@
 #define DEVID_STM32C03XX		0x453
 #define DEVID_STM32U53_U54XX	0x455
 #define DEVID_STM32G05_G06XX	0x456
+#define DEVID_STM32U031XX		0x459
 #define DEVID_STM32G07_G08XX	0x460
 #define DEVID_STM32L49_L4AXX	0x461
 #define DEVID_STM32L45_L46XX	0x462
@ -105,7 +106,9 @@
 #define DEVID_STM32G49_G4AXX	0x479
 #define DEVID_STM32U59_U5AXX	0x481
 #define DEVID_STM32U57_U58XX	0x482
+#define DEVID_STM32U073_U083XX	0x489
 #define DEVID_STM32WBA5X		0x492
+#define DEVID_STM32C071XX		0x493
 #define DEVID_STM32WB1XX		0x494
 #define DEVID_STM32WB5XX		0x495
 #define DEVID_STM32WB3XX		0x496
--- a/src/helper/list.h
+++ b/src/helper/list.h
@ -46,7 +46,7 @@ struct list_head {

 #define LIST_HEAD_INIT(name) { &(name), &(name) }

-#define LIST_HEAD(name) \
+#define OOCD_LIST_HEAD(name) \
 	struct list_head name = LIST_HEAD_INIT(name)

 static inline void
--- a/src/helper/log.h
+++ b/src/helper/log.h
@ -152,6 +152,9 @@ extern int debug_level;
 #define LOG_TARGET_INFO(target, fmt_str, ...) \
 	LOG_INFO("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)

+#define LOG_TARGET_USER(target, fmt_str, ...) \
+	LOG_USER("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
+
 #define LOG_TARGET_WARNING(target, fmt_str, ...) \
 	LOG_WARNING("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)

--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@ -10,10 +10,8 @@ noinst_LTLIBRARIES += %D%/libocdjtagdrivers.la
 %C%_libocdjtagdrivers_la_CPPFLAGS = $(AM_CPPFLAGS)

 ULINK_FIRMWARE = %D%/OpenULINK
-ANGIE_FILES = %D%/angie

 EXTRA_DIST += $(ULINK_FIRMWARE) \
-	$(ANGIE_FILES) \
 	%D%/usb_blaster/README.CheapClone \
 	%D%/Makefile.rlink \
 	%D%/rlink_call.m4 \
@ -125,12 +123,17 @@ ulinkdir = $(pkgdatadir)/OpenULINK
 dist_ulink_DATA = $(ULINK_FIRMWARE)/ulink_firmware.hex
 %C%_libocdjtagdrivers_la_LIBADD += -lm
 endif
+
 if ANGIE
-DRIVERFILES += %D%/angie.c
-angiedir = $(pkgdatadir)/angie
-dist_angie_DATA = $(ANGIE_FILES)/angie_firmware.bin $(ANGIE_FILES)/angie_bitstream.bit
-%C%_libocdjtagdrivers_la_LIBADD += -lm
+  angiedir = $(pkgdatadir)/angie  # This is only for dist_angie_DATA.
+  DRIVERFILES     += %D%/angie.c
+  DRIVERFILES     += %D%/angie/include/msgtypes.h
+  EXTRA_DIST      += %D%/angie/README
+  dist_angie_DATA  = %D%/angie/angie_firmware.bin
+  dist_angie_DATA += %D%/angie/angie_bitstream.bit
+  %C%_libocdjtagdrivers_la_LIBADD += -lm
 endif
+
 if VSLLINK
 DRIVERFILES += %D%/versaloon/usbtoxxx/usbtogpio.c
 DRIVERFILES += %D%/versaloon/usbtoxxx/usbtojtagraw.c
--- a/src/jtag/drivers/am335xgpio.c
+++ b/src/jtag/drivers/am335xgpio.c
@ -283,7 +283,7 @@ static int am335xgpio_blink(bool on)
 	return ERROR_OK;
 }

-static struct bitbang_interface am335xgpio_bitbang = {
+static const struct bitbang_interface am335xgpio_bitbang = {
 	.read = am335xgpio_read,
 	.write = am335xgpio_write,
 	.swdio_read = am335xgpio_swdio_read,
--- a/src/jtag/drivers/at91rm9200.c
+++ b/src/jtag/drivers/at91rm9200.c
@ -104,7 +104,7 @@ static int at91rm9200_write(int tck, int tms, int tdi);
 static int at91rm9200_init(void);
 static int at91rm9200_quit(void);

-static struct bitbang_interface at91rm9200_bitbang = {
+static const struct bitbang_interface at91rm9200_bitbang = {
 	.read = at91rm9200_read,
 	.write = at91rm9200_write,
 	.blink = NULL,
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@ -37,7 +37,7 @@ static int bitbang_stableclocks(unsigned int num_cycles);

 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk);

-struct bitbang_interface *bitbang_interface;
+const struct bitbang_interface *bitbang_interface;

 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
 *
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@ -67,6 +67,6 @@ extern const struct swd_driver bitbang_swd;

 int bitbang_execute_queue(struct jtag_command *cmd_queue);

-extern struct bitbang_interface *bitbang_interface;
+extern const struct bitbang_interface *bitbang_interface;

 #endif /* OPENOCD_JTAG_DRIVERS_BITBANG_H */
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@ -225,12 +225,6 @@ struct pending_scan_result {
 	unsigned int buffer_offset;
 };

-/* Read mode */
-enum cmsis_dap_blocking {
-	CMSIS_DAP_NON_BLOCKING,
-	CMSIS_DAP_BLOCKING
-};
-
 /* Each block in FIFO can contain up to pending_queue_len transfers */
 static unsigned int pending_queue_len;
 static unsigned int tfer_max_command_size;
@ -321,7 +315,7 @@ static void cmsis_dap_flush_read(struct cmsis_dap *dap)
 	 * USB close/open so we need to flush up to 64 old packets
 	 * to be sure all buffers are empty */
 	for (i = 0; i < 64; i++) {
-		int retval = dap->backend->read(dap, 10, NULL);
+		int retval = dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING);
 		if (retval == ERROR_TIMEOUT_REACHED)
 			break;
 	}
@ -338,7 +332,7 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen)
 	if (dap->pending_fifo_block_count) {
 		LOG_ERROR("pending %u blocks, flushing", dap->pending_fifo_block_count);
 		while (dap->pending_fifo_block_count) {
-			dap->backend->read(dap, 10, NULL);
+			dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING);
 			dap->pending_fifo_block_count--;
 		}
 		dap->pending_fifo_put_idx = 0;
@ -351,7 +345,7 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen)
 		return retval;

 	/* get reply */
-	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, NULL);
+	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, CMSIS_DAP_BLOCKING);
 	if (retval < 0)
 		return retval;

@ -885,7 +879,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blo

 	if (queued_retval != ERROR_OK) {
 		/* keep reading blocks until the pipeline is empty */
-		retval = dap->backend->read(dap, 10, NULL);
+		retval = dap->backend->read(dap, 10, CMSIS_DAP_BLOCKING);
 		if (retval == ERROR_TIMEOUT_REACHED || retval == 0) {
 			/* timeout means that we flushed the pipeline,
 			 * we can safely discard remaining pending requests */
@ -896,11 +890,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blo
 	}

 	/* get reply */
-	struct timeval tv = {
-		.tv_sec = 0,
-		.tv_usec = 0
-	};
-	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, blocking ? NULL : &tv);
+	retval = dap->backend->read(dap, LIBUSB_TIMEOUT_MS, blocking);
 	bool timeout = (retval == ERROR_TIMEOUT_REACHED || retval == 0);
 	if (timeout && blocking == CMSIS_DAP_NON_BLOCKING)
 		return;
--- a/src/jtag/drivers/cmsis_dap.h
+++ b/src/jtag/drivers/cmsis_dap.h
@ -58,12 +58,18 @@ struct cmsis_dap {
 	bool trace_enabled;
 };

+/* Read mode */
+enum cmsis_dap_blocking {
+	CMSIS_DAP_NON_BLOCKING,
+	CMSIS_DAP_BLOCKING
+};
+
 struct cmsis_dap_backend {
 	const char *name;
 	int (*open)(struct cmsis_dap *dap, uint16_t vids[], uint16_t pids[], const char *serial);
 	void (*close)(struct cmsis_dap *dap);
 	int (*read)(struct cmsis_dap *dap, int transfer_timeout_ms,
-			    struct timeval *wait_timeout);
+				enum cmsis_dap_blocking blocking);
 	int (*write)(struct cmsis_dap *dap, int len, int timeout_ms);
 	int (*packet_buffer_alloc)(struct cmsis_dap *dap, unsigned int pkt_sz);
 	void (*packet_buffer_free)(struct cmsis_dap *dap);
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@ -441,7 +441,7 @@ static void LIBUSB_CALL cmsis_dap_usb_callback(struct libusb_transfer *transfer)
 }

 static int cmsis_dap_usb_read(struct cmsis_dap *dap, int transfer_timeout_ms,
-							  struct timeval *wait_timeout)
+							  enum cmsis_dap_blocking blocking)
 {
 	int transferred = 0;
 	int err;
@ -464,20 +464,23 @@ static int cmsis_dap_usb_read(struct cmsis_dap *dap, int transfer_timeout_ms,
 		}
 	}

-	struct timeval tv = {
-		.tv_sec = transfer_timeout_ms / 1000,
-		.tv_usec = transfer_timeout_ms % 1000 * 1000
-	};
+	struct timeval tv;
+	if (blocking == CMSIS_DAP_NON_BLOCKING) {
+		tv.tv_sec = 0;
+		tv.tv_usec = 0;
+	} else {
+		tv.tv_sec = transfer_timeout_ms / 1000;
+		tv.tv_usec = transfer_timeout_ms % 1000 * 1000;
+	}

 	while (tr->status == CMSIS_DAP_TRANSFER_PENDING) {
-		err = libusb_handle_events_timeout_completed(dap->bdata->usb_ctx,
-												 wait_timeout ? wait_timeout : &tv,
+		err = libusb_handle_events_timeout_completed(dap->bdata->usb_ctx, &tv,
 												 &tr->status);
 		if (err) {
 			LOG_ERROR("error handling USB events: %s", libusb_strerror(err));
 			return ERROR_FAIL;
 		}
-		if (wait_timeout)
+		if (tv.tv_sec == 0 && tv.tv_usec == 0)
 			break;
 	}

@ -529,7 +532,7 @@ static int cmsis_dap_usb_write(struct cmsis_dap *dap, int txlen, int timeout_ms)
 	tr = &dap->bdata->command_transfers[dap->pending_fifo_put_idx];

 	if (tr->status == CMSIS_DAP_TRANSFER_PENDING) {
-		LOG_ERROR("busy command USB transfer at %u", dap->pending_fifo_put_idx);
+		LOG_DEBUG_IO("busy command USB transfer at %u", dap->pending_fifo_put_idx);
 		struct timeval tv = {
 			.tv_sec = timeout_ms / 1000,
 			.tv_usec = timeout_ms % 1000 * 1000
@ -544,7 +547,7 @@ static int cmsis_dap_usb_write(struct cmsis_dap *dap, int txlen, int timeout_ms)
 		tr->status = CMSIS_DAP_TRANSFER_IDLE;
 	}
 	if (tr->status == CMSIS_DAP_TRANSFER_COMPLETED) {
-		LOG_ERROR("USB write: late transfer competed");
+		LOG_DEBUG_IO("USB write: late transfer competed");
 		tr->status = CMSIS_DAP_TRANSFER_IDLE;
 	}
 	if (tr->status != CMSIS_DAP_TRANSFER_IDLE) {
--- a/src/jtag/drivers/cmsis_dap_usb_hid.c
+++ b/src/jtag/drivers/cmsis_dap_usb_hid.c
@ -206,17 +206,13 @@ static void cmsis_dap_hid_close(struct cmsis_dap *dap)
 }

 static int cmsis_dap_hid_read(struct cmsis_dap *dap, int transfer_timeout_ms,
-							  struct timeval *wait_timeout)
+							  enum cmsis_dap_blocking blocking)
 {
-	int timeout_ms;
-	if (wait_timeout)
-		timeout_ms = wait_timeout->tv_usec / 1000 + wait_timeout->tv_sec * 1000;
-	else
-		timeout_ms = transfer_timeout_ms;
+	int wait_ms = (blocking == CMSIS_DAP_NON_BLOCKING) ? 0 : transfer_timeout_ms;

 	int retval = hid_read_timeout(dap->bdata->dev_handle,
 								  dap->packet_buffer, dap->packet_buffer_size,
-								  timeout_ms);
+								  wait_ms);
 	if (retval == 0) {
 		return ERROR_TIMEOUT_REACHED;
 	} else if (retval == -1) {
--- a/src/jtag/drivers/dummy.c
+++ b/src/jtag/drivers/dummy.c
@ -77,7 +77,7 @@ static int dummy_led(bool on)
 	return ERROR_OK;
 }

-static struct bitbang_interface dummy_bitbang = {
+static const struct bitbang_interface dummy_bitbang = {
 		.read = &dummy_read,
 		.write = &dummy_write,
 		.blink = &dummy_led,
--- a/src/jtag/drivers/ep93xx.c
+++ b/src/jtag/drivers/ep93xx.c
@ -55,7 +55,7 @@ struct adapter_driver ep93xx_adapter_driver = {
 	.jtag_ops = &ep93xx_interface,
 };

-static struct bitbang_interface ep93xx_bitbang = {
+static const struct bitbang_interface ep93xx_bitbang = {
 	.read = ep93xx_read,
 	.write = ep93xx_write,
 	.blink = NULL,
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@ -82,7 +82,7 @@ static int imx_gpio_swd_write(int swclk, int swdio);
 static int imx_gpio_init(void);
 static int imx_gpio_quit(void);

-static struct bitbang_interface imx_gpio_bitbang = {
+static const struct bitbang_interface imx_gpio_bitbang = {
 	.read = imx_gpio_read,
 	.write = imx_gpio_write,
 	.swdio_read = imx_gpio_swdio_read,
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@ -191,7 +191,7 @@ static int linuxgpiod_blink(bool on)
 	return retval;
 }

-static struct bitbang_interface linuxgpiod_bitbang = {
+static const struct bitbang_interface linuxgpiod_bitbang = {
 	.read = linuxgpiod_read,
 	.write = linuxgpiod_write,
 	.swdio_read = linuxgpiod_swdio_read,
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@ -255,7 +255,7 @@ static int parport_get_giveio_access(void)
 }
 #endif

-static struct bitbang_interface parport_bitbang = {
+static const struct bitbang_interface parport_bitbang = {
 	.read = &parport_read,
 	.write = &parport_write,
 	.blink = &parport_led,
--- a/src/jtag/drivers/remote_bitbang.c
+++ b/src/jtag/drivers/remote_bitbang.c
@ -278,7 +278,7 @@ static int remote_bitbang_swd_write(int swclk, int swdio)
 	return remote_bitbang_queue(c, NO_FLUSH);
 }

-static struct bitbang_interface remote_bitbang_bitbang = {
+static const struct bitbang_interface remote_bitbang_bitbang = {
 	.buf_size = sizeof(remote_bitbang_recv_buf) - 1,
 	.sample = &remote_bitbang_sample,
 	.read_sample = &remote_bitbang_read_sample,
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@ -565,7 +565,7 @@ struct adapter_driver sysfsgpio_adapter_driver = {
 	.swd_ops = &bitbang_swd,
 };

-static struct bitbang_interface sysfsgpio_bitbang = {
+static const struct bitbang_interface sysfsgpio_bitbang = {
 	.read = sysfsgpio_read,
 	.write = sysfsgpio_write,
 	.swdio_read = sysfsgpio_swdio_read,
--- a/src/rtos/mqx.c
+++ b/src/rtos/mqx.c
@ -319,7 +319,7 @@ static int mqx_update_threads(
 		i < (uint32_t)rtos->thread_count;
 		i++
 	) {
-		uint8_t task_name[MQX_THREAD_NAME_LENGTH + 1];
+		char task_name[MQX_THREAD_NAME_LENGTH + 1];
 		uint32_t task_addr = 0, task_template = 0, task_state = 0;
 		uint32_t task_name_addr = 0, task_id = 0, task_errno = 0;
 		uint32_t state_index = 0;
@ -380,10 +380,9 @@ static int mqx_update_threads(
 		rtos->thread_details[i].threadid = task_id;
 		rtos->thread_details[i].exists = true;
 		/* set thread name */
-		rtos->thread_details[i].thread_name_str = malloc(strlen((void *)task_name) + 1);
+		rtos->thread_details[i].thread_name_str = strdup(task_name);
 		if (!rtos->thread_details[i].thread_name_str)
 			return ERROR_FAIL;
-		strcpy(rtos->thread_details[i].thread_name_str, (void *)task_name);
 		/* set thread extra info
 		 * - task state
 		 * - task address
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@ -635,7 +635,7 @@ int rtos_generic_stack_read(struct target *target,
 	int retval;

 	if (stack_ptr == 0) {
-		LOG_ERROR("Error: null stack pointer in thread");
+		LOG_ERROR("null stack pointer in thread");
 		return -5;
 	}
 	/* Read the stack */
--- a/src/server/rtt_server.c
+++ b/src/server/rtt_server.c
@ -28,6 +28,12 @@ struct rtt_service {
 	char *hello_message;
 };

+struct rtt_connection_data {
+	unsigned char buffer[64];
+	unsigned int length;
+	unsigned int offset;
+};
+
 static int read_callback(unsigned int channel, const uint8_t *buffer,
 		size_t length, void *user_data)
 {
@ -56,7 +62,16 @@ static int rtt_new_connection(struct connection *connection)
 {
 	int ret;
 	struct rtt_service *service;
+	struct rtt_connection_data *data;

+	data = calloc(1, sizeof(struct rtt_connection_data));
+
+	if (!data) {
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+
+	connection->priv = data;
 	service = connection->service->priv;

 	LOG_DEBUG("rtt: New connection for channel %u", service->channel);
@ -79,31 +94,53 @@ static int rtt_connection_closed(struct connection *connection)
 	service = (struct rtt_service *)connection->service->priv;
 	rtt_unregister_sink(service->channel, &read_callback, connection);

-	LOG_DEBUG("rtt: Connection for channel %u closed", service->channel);
+	free(connection->priv);

+	LOG_DEBUG("rtt: Connection for channel %u closed", service->channel);
 	return ERROR_OK;
 }

 static int rtt_input(struct connection *connection)
 {
-	int bytes_read;
-	unsigned char buffer[1024];
 	struct rtt_service *service;
-	size_t length;
+	struct rtt_connection_data *data;

-	service = (struct rtt_service *)connection->service->priv;
-	bytes_read = connection_read(connection, buffer, sizeof(buffer));
+	data = connection->priv;
+	service = connection->service->priv;

-	if (!bytes_read)
-		return ERROR_SERVER_REMOTE_CLOSED;
-	else if (bytes_read < 0) {
-		LOG_ERROR("error during read: %s", strerror(errno));
-		return ERROR_SERVER_REMOTE_CLOSED;
+	if (!connection->input_pending) {
+		int bytes_read;
+
+		bytes_read = connection_read(connection, data->buffer, sizeof(data->buffer));
+
+		if (!bytes_read) {
+			return ERROR_SERVER_REMOTE_CLOSED;
+		} else if (bytes_read < 0) {
+			LOG_ERROR("error during read: %s", strerror(errno));
+			return ERROR_SERVER_REMOTE_CLOSED;
+		}
+
+		data->length = bytes_read;
+		data->offset = 0;
 	}
+	if (data->length > 0) {
+		unsigned char *ptr;
+		size_t length, to_write;

-	length = bytes_read;
-	rtt_write_channel(service->channel, buffer, &length);
+		ptr = data->buffer + data->offset;
+		length = data->length - data->offset;
+		to_write = length;
+		rtt_write_channel(service->channel, ptr, &length);

+		if (length < to_write) {
+			data->offset += length;
+			connection->input_pending = true;
+		} else {
+			data->offset = 0;
+			data->length = 0;
+			connection->input_pending = false;
+		}
+	}
 	return ERROR_OK;
 }

@ -126,8 +163,10 @@ COMMAND_HANDLER(handle_rtt_start_command)

 	service = calloc(1, sizeof(struct rtt_service));

-	if (!service)
+	if (!service) {
+		LOG_ERROR("Out of memory");
 		return ERROR_FAIL;
+	}

 	COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], service->channel);

--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@ -570,7 +570,7 @@ static void telnet_auto_complete(struct connection *connection)
 		struct list_head lh;
 	};

-	LIST_HEAD(matches);
+	OOCD_LIST_HEAD(matches);

 	/* - user command sequence, either at line beginning
 	 *   or we start over after these characters ';', '[', '{'
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@ -431,7 +431,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
 	struct dap_cmd *el, *tmp, *prev = NULL;
 	int found_wait = 0;
 	int64_t time_now;
-	LIST_HEAD(replay_list);
+	OOCD_LIST_HEAD(replay_list);

 	/* make sure all queued transactions are complete */
 	retval = jtag_execute_queue();
--- a/src/target/arc.c
+++ b/src/target/arc.c
@ -61,7 +61,7 @@ static int arc_single_step_core(struct target *target);
 void arc_reg_data_type_add(struct target *target,
 		struct arc_reg_data_type *data_type)
 {
-	LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
+	LOG_TARGET_DEBUG(target, "Adding %s reg_data_type", data_type->data_type.id);
 	struct arc_common *arc = target_to_arc(target);
 	assert(arc);

@ -104,7 +104,7 @@ static int arc_reset_caches_states(struct target *target)
 {
 	struct arc_common *arc = target_to_arc(target);

-	LOG_DEBUG("Resetting internal variables of caches states");
+	LOG_TARGET_DEBUG(target, "Resetting internal variables of caches states");

 	/* Reset caches states. */
 	arc->dcache_flushed = false;
@ -127,7 +127,7 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc,

 	/* The only allowed ir_length is 4 for ARC jtag. */
 	if (tap->ir_length != 4) {
-		LOG_ERROR("ARC jtag instruction length should be equal to 4");
+		LOG_TARGET_ERROR(target, "ARC jtag instruction length should be equal to 4");
 		return ERROR_FAIL;
 	}

@ -146,7 +146,7 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc,
 		sizeof(*std_types));

 	if (!std_types) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}

@ -205,7 +205,7 @@ int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 	}
 	arc->num_regs += 1;

-	LOG_DEBUG(
+	LOG_TARGET_DEBUG(target,
 			"added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
 			arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
 			arc_reg->is_core ? ", core" : "",  arc_reg->is_bcr ? ", bcr" : "",
@ -227,7 +227,7 @@ static int arc_get_register(struct reg *reg)
 	uint32_t value;

 	if (reg->valid) {
-		LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 				reg->number, desc->name, target_buffer_get_u32(target, reg->value));
 		return ERROR_OK;
 	}
@ -235,7 +235,7 @@ static int arc_get_register(struct reg *reg)
 	if (desc->is_core) {
 		/* Accessing to R61/R62 registers causes Jtag hang */
 		if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) {
-			LOG_ERROR("It is forbidden to read core registers 61 and 62.");
+			LOG_TARGET_ERROR(target, "It is forbidden to read core registers 61 and 62");
 			return ERROR_FAIL;
 		}
 		CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
@ -255,7 +255,7 @@ static int arc_get_register(struct reg *reg)

 	reg->dirty = false;

-	LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+	LOG_TARGET_DEBUG(target, "Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 			reg->number, desc->name, value);


@ -276,12 +276,12 @@ static int arc_set_register(struct reg *reg, uint8_t *buf)
 	/* Accessing to R61/R62 registers causes Jtag hang */
 	if (desc->is_core && (desc->arch_num == ARC_R61 ||
 			desc->arch_num == ARC_R62)) {
-		LOG_ERROR("It is forbidden to write core registers 61 and 62.");
+		LOG_TARGET_ERROR(target, "It is forbidden to write core registers 61 and 62");
 		return ERROR_FAIL;
 	}
 	target_buffer_set_u32(target, reg->value, value);

-	LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+	LOG_TARGET_DEBUG(target, "Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
 			reg->number, desc->name, value);

 	reg->valid = true;
@ -355,7 +355,7 @@ static int arc_build_reg_cache(struct target *target)
 	struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));

 	if (!cache || !reg_list)  {
-		LOG_ERROR("Not enough memory");
+		LOG_TARGET_ERROR(target, "Not enough memory");
 		goto fail;
 	}

@ -368,14 +368,14 @@ static int arc_build_reg_cache(struct target *target)
 	(*cache_p) = cache;

 	if (list_empty(&arc->core_reg_descriptions)) {
-		LOG_ERROR("No core registers were defined");
+		LOG_TARGET_ERROR(target, "No core registers were defined");
 		goto fail;
 	}

 	list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
 		CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));

-		LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
 			reg_list[i].feature->name);

@ -383,27 +383,27 @@ static int arc_build_reg_cache(struct target *target)
 	}

 	if (list_empty(&arc->aux_reg_descriptions)) {
-		LOG_ERROR("No aux registers were defined");
+		LOG_TARGET_ERROR(target, "No aux registers were defined");
 		goto fail;
 	}

 	list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
 		 CHECK_RETVAL(arc_init_reg(target, &reg_list[i],  reg_desc, i));

-		LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
 			reg_list[i].feature->name);

 		/* PC and DEBUG are essential so we search for them. */
 		if (!strcmp("pc", reg_desc->name)) {
 			if (arc->pc_index_in_cache != ULONG_MAX) {
-				LOG_ERROR("Double definition of PC in configuration");
+				LOG_TARGET_ERROR(target, "Double definition of PC in configuration");
 				goto fail;
 			}
 			arc->pc_index_in_cache = i;
 		} else if (!strcmp("debug", reg_desc->name)) {
 			if (arc->debug_index_in_cache != ULONG_MAX) {
-				LOG_ERROR("Double definition of DEBUG in configuration");
+				LOG_TARGET_ERROR(target, "Double definition of DEBUG in configuration");
 				goto fail;
 			}
 			arc->debug_index_in_cache = i;
@ -413,7 +413,7 @@ static int arc_build_reg_cache(struct target *target)

 	if (arc->pc_index_in_cache == ULONG_MAX
 			|| arc->debug_index_in_cache == ULONG_MAX) {
-		LOG_ERROR("`pc' and `debug' registers must be present in target description.");
+		LOG_TARGET_ERROR(target, "`pc' and `debug' registers must be present in target description");
 		goto fail;
 	}

@ -446,7 +446,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 	unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;

 	if (!cache || !reg_list)  {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		goto fail;
 	}

@ -459,7 +459,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 	(*cache_p) = cache;

 	if (list_empty(&arc->bcr_reg_descriptions)) {
-		LOG_ERROR("No BCR registers are defined");
+		LOG_TARGET_ERROR(target, "No BCR registers are defined");
 		goto fail;
 	}

@ -469,7 +469,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 		 * not real register. */
 		reg_list[i].exist = true;

-		LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
 			reg_list[i].feature->name);
 		i += 1;
@ -501,7 +501,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 	*reg_list = calloc(*reg_list_size, sizeof(struct reg *));

 	if (!*reg_list) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}

@ -521,7 +521,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 			reg_cache = reg_cache->next;
 		}
 		assert(i == arc->num_regs);
-		LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
+		LOG_TARGET_DEBUG(target, "REG_CLASS_ALL: number of regs=%i", *reg_list_size);
 	} else {
 		unsigned long i = 0;
 		unsigned long gdb_reg_number = 0;
@ -539,7 +539,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 			reg_cache = reg_cache->next;
 		}
 		*reg_list_size = i;
-		LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
+		LOG_TARGET_DEBUG(target, "REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
 	}

 	return ERROR_OK;
@ -551,13 +551,13 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
 {
 	struct reg_data_type_struct_field *field;

-	LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
+	LOG_TARGET_DEBUG(target, "getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);

 	/* Get register */
 	struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);

 	if (!reg) {
-		LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
+		LOG_TARGET_ERROR(target, "Requested register `%s' doesn't exist", reg_name);
 		return ERROR_ARC_REGISTER_NOT_FOUND;
 	}

@ -597,7 +597,7 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
 static int arc_get_register_value(struct target *target, const char *reg_name,
 		uint32_t *value_ptr)
 {
-	LOG_DEBUG("reg_name=%s", reg_name);
+	LOG_TARGET_DEBUG(target, "reg_name=%s", reg_name);

 	struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);

@ -615,10 +615,10 @@ static int arc_get_register_value(struct target *target, const char *reg_name,
 static int arc_set_register_value(struct target *target, const char *reg_name,
 		uint32_t value)
 {
-	LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
+	LOG_TARGET_DEBUG(target, "reg_name=%s value=0x%08" PRIx32, reg_name, value);

 	if (!(target && reg_name)) {
-		LOG_ERROR("Arguments cannot be NULL.");
+		LOG_TARGET_ERROR(target, "Arguments cannot be NULL");
 		return ERROR_FAIL;
 	}

@ -655,7 +655,7 @@ static int arc_configure_dccm(struct target  *target)
 		if (dccm_build_size0 == 0xF)
 			dccm_size <<= dccm_build_size1;
 		arc->dccm_end = arc->dccm_start + dccm_size;
-		LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
 				arc->dccm_start, arc->dccm_end);

 	}
@ -687,7 +687,7 @@ static int arc_configure_iccm(struct target  *target)
 		/* iccm0 start is located in highest 4 bits of aux_iccm */
 		arc->iccm0_start = aux_iccm & 0xF0000000;
 		arc->iccm0_end = arc->iccm0_start + iccm0_size;
-		LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 				arc->iccm0_start, arc->iccm0_end);
 	}

@ -707,7 +707,7 @@ static int arc_configure_iccm(struct target  *target)
 			iccm1_size <<= iccm_build_size11;
 		arc->iccm1_start = aux_iccm & 0x0F000000;
 		arc->iccm1_end = arc->iccm1_start + iccm1_size;
-		LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 				arc->iccm1_start, arc->iccm1_end);
 	}
 	return ERROR_OK;
@ -716,7 +716,7 @@ static int arc_configure_iccm(struct target  *target)
 /* Configure some core features, depending on BCRs. */
 static int arc_configure(struct target *target)
 {
-	LOG_DEBUG("Configuring ARC ICCM and DCCM");
+	LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");

 	/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
 	if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
@ -770,9 +770,9 @@ static int arc_exit_debug(struct target *target)
 	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));

 	if (debug_level >= LOG_LVL_DEBUG) {
-		LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core stopped (halted) debug-reg: 0x%08" PRIx32, value);
 		CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
-		LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value);
 	}

 	return ERROR_OK;
@ -783,19 +783,19 @@ static int arc_halt(struct target *target)
 	uint32_t value, irq_state;
 	struct arc_common *arc = target_to_arc(target);

-	LOG_DEBUG("target->state: %s", target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));

 	if (target->state == TARGET_HALTED) {
-		LOG_DEBUG("target was already halted");
+		LOG_TARGET_DEBUG(target, "target was already halted");
 		return ERROR_OK;
 	}

 	if (target->state == TARGET_UNKNOWN)
-		LOG_WARNING("target was in unknown state when halt was requested");
+		LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");

 	if (target->state == TARGET_RESET) {
 		if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
-			LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
+			LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
 			return ERROR_TARGET_FAILURE;
 		} else {
 			target->debug_reason = DBG_REASON_DBGRQ;
@ -825,9 +825,9 @@ static int arc_halt(struct target *target)

 	/* some more debug information */
 	if (debug_level >= LOG_LVL_DEBUG) {
-		LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
 		CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
-		LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value);
 	}

 	return ERROR_OK;
@ -846,7 +846,7 @@ static int arc_save_context(struct target *target)
 	struct arc_common *arc = target_to_arc(target);
 	struct reg *reg_list = arc->core_and_aux_cache->reg_list;

-	LOG_DEBUG("Saving aux and core registers values");
+	LOG_TARGET_DEBUG(target, "Saving aux and core registers values");
 	assert(reg_list);

 	/* It is assumed that there is at least one AUX register in the list, for
@ -865,7 +865,7 @@ static int arc_save_context(struct target *target)
 	unsigned int aux_cnt = 0;

 	if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		retval = ERROR_FAIL;
 		goto exit;
 	}
@ -893,7 +893,7 @@ static int arc_save_context(struct target *target)
 	if (core_cnt > 0) {
 		retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to read core registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to read core registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@ -901,7 +901,7 @@ static int arc_save_context(struct target *target)
 	if (aux_cnt > 0) {
 		retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to read aux registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to read aux registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@ -916,7 +916,7 @@ static int arc_save_context(struct target *target)
 			target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
 			reg->valid = true;
 			reg->dirty = false;
-			LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
+			LOG_TARGET_DEBUG(target, "Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
 				i, arc_reg->name, core_values[core_cnt]);
 			core_cnt++;
 		}
@ -931,7 +931,7 @@ static int arc_save_context(struct target *target)
 			target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
 			reg->valid = true;
 			reg->dirty = false;
-			LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
+			LOG_TARGET_DEBUG(target, "Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
 				i, arc_reg->name, aux_values[aux_cnt]);
 			aux_cnt++;
 		}
@ -1009,14 +1009,14 @@ static int arc_examine_debug_reason(struct target *target)

 		if (actionpoint) {
 			if (!actionpoint->used)
-				LOG_WARNING("Target halted by an unused actionpoint.");
+				LOG_TARGET_WARNING(target, "Target halted by an unused actionpoint");

 			if (actionpoint->type == ARC_AP_BREAKPOINT)
 				target->debug_reason = DBG_REASON_BREAKPOINT;
 			else if (actionpoint->type == ARC_AP_WATCHPOINT)
 				target->debug_reason = DBG_REASON_WATCHPOINT;
 			else
-				LOG_WARNING("Unknown type of actionpoint.");
+				LOG_TARGET_WARNING(target, "Unknown type of actionpoint");
 		}
 	}

@ -1046,7 +1046,7 @@ static int arc_poll(struct target *target)
 	/* check for processor halted */
 	if (status & ARC_JTAG_STAT_RU) {
 		if (target->state != TARGET_RUNNING) {
-			LOG_WARNING("target is still running!");
+			LOG_TARGET_WARNING(target, "target is still running");
 			target->state = TARGET_RUNNING;
 		}
 		return ERROR_OK;
@ -1057,21 +1057,21 @@ static int arc_poll(struct target *target)
 	if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
 		CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
 		if (value & AUX_STATUS32_REG_HALT_BIT) {
-			LOG_DEBUG("ARC core in halt or reset state.");
+			LOG_TARGET_DEBUG(target, "ARC core in halt or reset state");
 			/* Save context if target was not in reset state */
 			if (target->state == TARGET_RUNNING)
 				CHECK_RETVAL(arc_debug_entry(target));
 			target->state = TARGET_HALTED;
 			CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 		} else {
-		LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
+			LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
 						"target is still running");
 		}

 	} else if (target->state == TARGET_DEBUG_RUNNING) {

 		target->state = TARGET_HALTED;
-		LOG_DEBUG("ARC core is in debug running mode");
+		LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");

 		CHECK_RETVAL(arc_debug_entry(target));

@ -1087,7 +1087,7 @@ static int arc_assert_reset(struct target *target)
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	bool srst_asserted = false;

-	LOG_DEBUG("target->state: %s", target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));

 	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 		/* allow scripts to override the reset event */
@ -1101,7 +1101,7 @@ static int arc_assert_reset(struct target *target)
 		if (target->state == TARGET_HALTED && !target->reset_halt) {
 			/* Resume the target and continue from the current
 			 * PC register value. */
-			LOG_DEBUG("Starting CPU execution after reset");
+			LOG_TARGET_DEBUG(target, "Starting CPU execution after reset");
 			CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
 		}
 		target->state = TARGET_RESET;
@ -1138,7 +1138,7 @@ static int arc_assert_reset(struct target *target)

 static int arc_deassert_reset(struct target *target)
 {
-	LOG_DEBUG("target->state: %s", target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));

 	/* deassert reset lines */
 	jtag_add_reset(0, 0);
@ -1155,7 +1155,7 @@ static int arc_arch_state(struct target *target)

 	CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));

-	LOG_DEBUG("target state: %s;  PC at: 0x%08" PRIx32,
+	LOG_TARGET_DEBUG(target, "target state: %s;  PC at: 0x%08" PRIx32,
 		target_state_name(target),
 		pc_value);

@ -1174,7 +1174,7 @@ static int arc_restore_context(struct target *target)
 	struct arc_common *arc = target_to_arc(target);
 	struct reg *reg_list = arc->core_and_aux_cache->reg_list;

-	LOG_DEBUG("Restoring registers values");
+	LOG_TARGET_DEBUG(target, "Restoring registers values");
 	assert(reg_list);

 	const uint32_t core_regs_size = arc->num_core_regs  * sizeof(uint32_t);
@ -1187,7 +1187,7 @@ static int arc_restore_context(struct target *target)
 	unsigned int aux_cnt = 0;

 	if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		retval = ERROR_FAIL;
 		goto exit;
 	}
@ -1201,7 +1201,7 @@ static int arc_restore_context(struct target *target)
 		struct reg *reg = &(reg_list[i]);
 		struct arc_reg_desc *arc_reg = reg->arch_info;
 		if (reg->valid && reg->exist && reg->dirty) {
-			LOG_DEBUG("Will write regnum=%u", i);
+			LOG_TARGET_DEBUG(target, "Will write regnum=%u", i);
 			core_addrs[core_cnt] = arc_reg->arch_num;
 			core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
 			core_cnt += 1;
@ -1212,7 +1212,7 @@ static int arc_restore_context(struct target *target)
 		struct reg *reg = &(reg_list[arc->num_core_regs + i]);
 		struct arc_reg_desc *arc_reg = reg->arch_info;
 		if (reg->valid && reg->exist && reg->dirty) {
-			LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
+			LOG_TARGET_DEBUG(target, "Will write regnum=%lu", arc->num_core_regs + i);
 			aux_addrs[aux_cnt] = arc_reg->arch_num;
 			aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
 			aux_cnt += 1;
@ -1224,7 +1224,7 @@ static int arc_restore_context(struct target *target)
 	if (core_cnt > 0) {
 		retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to write to core registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to write to core registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@ -1233,7 +1233,7 @@ static int arc_restore_context(struct target *target)
 	if (aux_cnt > 0) {
 		retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Attempt to write to aux registers failed.");
+			LOG_TARGET_ERROR(target, "Attempt to write to aux registers failed");
 			retval = ERROR_FAIL;
 			goto exit;
 		}
@ -1260,12 +1260,12 @@ static int arc_enable_interrupts(struct target *target, int enable)
 		/* enable interrupts */
 		value |= SET_CORE_ENABLE_INTERRUPTS;
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
-		LOG_DEBUG("interrupts enabled");
+		LOG_TARGET_DEBUG(target, "interrupts enabled");
 	} else {
 		/* disable interrupts */
 		value &= ~SET_CORE_ENABLE_INTERRUPTS;
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
-		LOG_DEBUG("interrupts disabled");
+		LOG_TARGET_DEBUG(target, "interrupts disabled");
 	}

 	return ERROR_OK;
@ -1279,7 +1279,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	uint32_t value;
 	struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];

-	LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
+	LOG_TARGET_DEBUG(target, "current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
 		" debug_execution:%i", current, address, handle_breakpoints, debug_execution);

 	/* We need to reset ARC cache variables so caches
@ -1304,7 +1304,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 		target_buffer_set_u32(target, pc->value, address);
 		pc->dirty = true;
 		pc->valid = true;
-		LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
+		LOG_TARGET_DEBUG(target, "Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
 	}

 	if (!current)
@ -1314,13 +1314,13 @@ static int arc_resume(struct target *target, int current, target_addr_t address,

 	CHECK_RETVAL(arc_restore_context(target));

-	LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
+	LOG_TARGET_DEBUG(target, "Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
 		resume_pc, pc->dirty, pc->valid);

 	/* check if GDB tells to set our PC where to continue from */
 	if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) {
 		value = target_buffer_get_u32(target, pc->value);
-		LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
+		LOG_TARGET_DEBUG(target, "resume Core (when start-core) with PC @:0x%08" PRIx32, value);
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
 	}

@ -1329,7 +1329,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 		/* Single step past breakpoint at current address */
 		struct breakpoint *breakpoint = breakpoint_find(target, resume_pc);
 		if (breakpoint) {
-			LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
+			LOG_TARGET_DEBUG(target, "skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
 				breakpoint->address);
 			CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
 			CHECK_RETVAL(arc_single_step_core(target));
@ -1350,7 +1350,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
 	value &= ~SET_CORE_HALT_BIT;        /* clear the HALT bit */
 	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
-	LOG_DEBUG("Core started to run");
+	LOG_TARGET_DEBUG(target, "Core started to run");

 	/* registers are now invalid */
 	register_cache_invalidate(arc->core_and_aux_cache);
@ -1358,11 +1358,11 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	if (!debug_execution) {
 		target->state = TARGET_RUNNING;
 		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
-		LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
+		LOG_TARGET_DEBUG(target, "target resumed at 0x%08" PRIx32, resume_pc);
 	} else {
 		target->state = TARGET_DEBUG_RUNNING;
 		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
-		LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
+		LOG_TARGET_DEBUG(target, "target debug resumed at 0x%08" PRIx32, resume_pc);
 	}

 	return ERROR_OK;
@ -1386,7 +1386,7 @@ static void arc_deinit_target(struct target *target)
 {
 	struct arc_common *arc = target_to_arc(target);

-	LOG_DEBUG("deinitialization of target");
+	LOG_TARGET_DEBUG(target, "deinitialization of target");
 	if (arc->core_aux_cache_built)
 		arc_free_reg_cache(arc->core_and_aux_cache);
 	if (arc->bcr_cache_built)
@ -1431,11 +1431,11 @@ static int arc_target_create(struct target *target, Jim_Interp *interp)
 	struct arc_common *arc = calloc(1, sizeof(*arc));

 	if (!arc) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}

-	LOG_DEBUG("Entering");
+	LOG_TARGET_DEBUG(target, "Entering");
 	CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));

 	return ERROR_OK;
@ -1452,11 +1452,11 @@ static int arc_write_instruction_u32(struct target *target, uint32_t address,
 {
 	uint8_t value_buf[4];
 	if (!target_was_examined(target)) {
-		LOG_ERROR("Target not examined yet");
+		LOG_TARGET_ERROR(target, "Target not examined yet");
 		return ERROR_FAIL;
 	}

-	LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
+	LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
 		instr);

 	if (target->endianness == TARGET_LITTLE_ENDIAN)
@ -1480,7 +1480,7 @@ static int arc_read_instruction_u32(struct target *target, uint32_t address,
 	uint8_t value_buf[4];

 	if (!target_was_examined(target)) {
-		LOG_ERROR("Target not examined yet");
+		LOG_TARGET_ERROR(target, "Target not examined yet");
 		return ERROR_FAIL;
 	}

@ -1492,7 +1492,7 @@ static int arc_read_instruction_u32(struct target *target, uint32_t address,
 	else
 		*value = be_to_h_u32(value_buf);

-	LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
+	LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
 		*value);

 	return ERROR_OK;
@ -1513,7 +1513,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
 	if (control_tt != AP_AC_TT_DISABLE) {

 		if (arc->actionpoints_num_avail < 1) {
-			LOG_ERROR("No free actionpoints, maximum amount is %u",
+			LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
 					arc->actionpoints_num);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@ -1547,12 +1547,12 @@ static int arc_set_breakpoint(struct target *target,
 		struct breakpoint *breakpoint)
 {
 	if (breakpoint->is_set) {
-		LOG_WARNING("breakpoint already set");
+		LOG_TARGET_WARNING(target, "breakpoint already set");
 		return ERROR_OK;
 	}

 	if (breakpoint->type == BKPT_SOFT) {
-		LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
+		LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id);

 		if (breakpoint->length == 4) {
 			uint32_t verify = 0xffffffff;
@ -1566,7 +1566,7 @@ static int arc_set_breakpoint(struct target *target,
 			CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));

 			if (verify != ARC_SDBBP_32) {
-				LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
+				LOG_TARGET_ERROR(target, "Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
 						" - check that memory is read/writable", breakpoint->address);
 				return ERROR_FAIL;
 			}
@ -1579,12 +1579,12 @@ static int arc_set_breakpoint(struct target *target,

 			CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
 			if (verify != ARC_SDBBP_16) {
-				LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
+				LOG_TARGET_ERROR(target, "Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
 						" - check that memory is read/writable", breakpoint->address);
 				return ERROR_FAIL;
 			}
 		} else {
-			LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
+			LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}

@ -1600,7 +1600,7 @@ static int arc_set_breakpoint(struct target *target,
 		}

 		if (bp_num >= arc->actionpoints_num) {
-			LOG_ERROR("No free actionpoints, maximum amount is %u",
+			LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
 					arc->actionpoints_num);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@ -1614,12 +1614,12 @@ static int arc_set_breakpoint(struct target *target,
 			ap_list[bp_num].bp_value = breakpoint->address;
 			ap_list[bp_num].type = ARC_AP_BREAKPOINT;

-			LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
+			LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
 					breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
 		}

 	} else {
-		LOG_DEBUG("ERROR: setting unknown breakpoint type");
+		LOG_TARGET_ERROR(target, "setting unknown breakpoint type");
 		return ERROR_FAIL;
 	}

@ -1632,13 +1632,13 @@ static int arc_unset_breakpoint(struct target *target,
 	int retval = ERROR_OK;

 	if (!breakpoint->is_set) {
-		LOG_WARNING("breakpoint not set");
+		LOG_TARGET_WARNING(target, "breakpoint not set");
 		return ERROR_OK;
 	}

 	if (breakpoint->type == BKPT_SOFT) {
 		/* restore original instruction (kept in target endianness) */
-		LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
+		LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id);
 		if (breakpoint->length == 4) {
 			uint32_t current_instr;

@ -1651,7 +1651,7 @@ static int arc_unset_breakpoint(struct target *target,
 				if (retval != ERROR_OK)
 					return retval;
 			} else {
-				LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
+				LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR
 					" has been overwritten outside of debugger."
 					"Expected: @0x%x, got: @0x%" PRIx32,
 					breakpoint->address, ARC_SDBBP_32, current_instr);
@ -1667,24 +1667,24 @@ static int arc_unset_breakpoint(struct target *target,
 				if (retval != ERROR_OK)
 					return retval;
 			} else {
-				LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
+				LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR
 					" has been overwritten outside of debugger. "
 					"Expected: 0x%04x, got: 0x%04" PRIx16,
 					breakpoint->address, ARC_SDBBP_16, current_instr);
 			}
 		} else {
-			LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
+			LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4");
 			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
 		breakpoint->is_set = false;

-	}	else if (breakpoint->type == BKPT_HARD) {
+	} else if (breakpoint->type == BKPT_HARD) {
 		struct arc_common *arc = target_to_arc(target);
 		struct arc_actionpoint *ap_list = arc->actionpoints_list;
 		unsigned int bp_num = breakpoint->number;

 		if (bp_num >= arc->actionpoints_num) {
-			LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
+			LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
 					  bp_num, breakpoint->unique_id);
 			return ERROR_OK;
 		}
@ -1697,12 +1697,12 @@ static int arc_unset_breakpoint(struct target *target,
 			ap_list[bp_num].used = 0;
 			ap_list[bp_num].bp_value = 0;

-			LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
+			LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 " - released actionpoint ID: %u",
 					breakpoint->unique_id, bp_num);
 		}
 	} else {
-			LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
-			return ERROR_FAIL;
+		LOG_TARGET_ERROR(target, "unsetting unknown breakpoint type");
+		return ERROR_FAIL;
 	}

 	return retval;
@ -1775,7 +1775,7 @@ static void arc_reset_actionpoints(struct target *target)

 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
 {
-	LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
+	LOG_TARGET_DEBUG(target, "actionpoints=%" PRIu32, ap_num);
 	struct arc_common *arc = target_to_arc(target);

 	/* Make sure that there are no enabled actionpoints in target. */
@ -1790,7 +1790,7 @@ int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
 	arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));

 	if (!arc->actionpoints_list) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		return ERROR_FAIL;
 	}
 	return ERROR_OK;
@ -1813,7 +1813,7 @@ int arc_add_auxreg_actionpoint(struct target *target,
 		ap_num++;

 	if (ap_num >= arc->actionpoints_num) {
-		LOG_ERROR("No actionpoint free, maximum amount is %u",
+		LOG_TARGET_ERROR(target, "No actionpoint free, maximum amount is %u",
 				arc->actionpoints_num);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
@ -1858,7 +1858,7 @@ int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
 			ap_list[ap_num].bp_value = 0;
 		}
 	} else {
-		LOG_ERROR("Register actionpoint not found");
+		LOG_TARGET_ERROR(target, "Register actionpoint not found");
 	}
 	return retval;
 }
@ -1872,7 +1872,7 @@ static int arc_set_watchpoint(struct target *target,
 	struct arc_actionpoint *ap_list = arc->actionpoints_list;

 	if (watchpoint->is_set) {
-		LOG_WARNING("watchpoint already set");
+		LOG_TARGET_WARNING(target, "watchpoint already set");
 		return ERROR_OK;
 	}

@ -1882,13 +1882,13 @@ static int arc_set_watchpoint(struct target *target,
 	}

 	if (wp_num >= arc->actionpoints_num) {
-		LOG_ERROR("No free actionpoints, maximum amount is %u",
+		LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
 				arc->actionpoints_num);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}

 	if (watchpoint->length != 4) {
-		LOG_ERROR("Only watchpoints of length 4 are supported");
+		LOG_TARGET_ERROR(target, "Only watchpoints of length 4 are supported");
 		return ERROR_TARGET_UNALIGNED_ACCESS;
 	}

@ -1904,7 +1904,7 @@ static int arc_set_watchpoint(struct target *target,
 			enable = AP_AC_TT_READWRITE;
 			break;
 		default:
-			LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
+			LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access");
 			return ERROR_FAIL;
 	}

@ -1917,7 +1917,7 @@ static int arc_set_watchpoint(struct target *target,
 		ap_list[wp_num].bp_value = watchpoint->address;
 		ap_list[wp_num].type = ARC_AP_WATCHPOINT;

-		LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
+		LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
 				watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value);
 	}

@ -1932,13 +1932,13 @@ static int arc_unset_watchpoint(struct target *target,
 	struct arc_actionpoint *ap_list = arc->actionpoints_list;

 	if (!watchpoint->is_set) {
-		LOG_WARNING("watchpoint not set");
+		LOG_TARGET_WARNING(target, "watchpoint not set");
 		return ERROR_OK;
 	}

 	unsigned int wp_num = watchpoint->number;
 	if (wp_num >= arc->actionpoints_num) {
-		LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
+		LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
 				wp_num, watchpoint->unique_id);
 		return ERROR_OK;
 	}
@ -1951,7 +1951,7 @@ static int arc_unset_watchpoint(struct target *target,
 		ap_list[wp_num].used = 0;
 		ap_list[wp_num].bp_value = 0;

-		LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
+		LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 " - releasing actionpoint ID: %u",
 				watchpoint->unique_id, wp_num);
 	}

@ -2009,18 +2009,18 @@ static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_wat

 	if (actionpoint) {
 		if (!actionpoint->used)
-			LOG_WARNING("Target halted by unused actionpoint.");
+			LOG_TARGET_WARNING(target, "Target halted by unused actionpoint");

 		/* If this check fails - that is some sort of an error in OpenOCD. */
 		if (actionpoint->type != ARC_AP_WATCHPOINT)
-			LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
+			LOG_TARGET_WARNING(target, "Target halted by breakpoint, but is treated as a watchpoint");

 		for (struct watchpoint *watchpoint = target->watchpoints;
 				watchpoint;
 				watchpoint = watchpoint->next) {
 			if (actionpoint->bp_value == watchpoint->address) {
 				*hit_watchpoint = watchpoint;
-				LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
+				LOG_TARGET_DEBUG(target, "Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
 							watchpoint->unique_id, watchpoint->number);
 				return ERROR_OK;
 			}
@ -2045,7 +2045,7 @@ static int arc_config_step(struct target *target, int enable_step)
 		value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
 			value));
-		LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
+		LOG_TARGET_DEBUG(target, " [status32:0x%08" PRIx32 "]", value);

 		/* Doing read-modify-write, because DEBUG might contain manually set
 		 * bits like UB or ED, which should be preserved.  */
@ -2054,7 +2054,7 @@ static int arc_config_step(struct target *target, int enable_step)
 		value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
 			value));
-		LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
+		LOG_TARGET_DEBUG(target, "core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);

 	} else {	/* disable core debug step mode */
 		CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
@ -2062,7 +2062,7 @@ static int arc_config_step(struct target *target, int enable_step)
 		value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
 			value));
-		LOG_DEBUG("core debug step mode disabled");
+		LOG_TARGET_DEBUG(target, "core debug step mode disabled");
 	}

 	return ERROR_OK;
@ -2104,7 +2104,7 @@ static int arc_step(struct target *target, int current, target_addr_t address,
 		pc->valid = true;
 	}

-	LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
+	LOG_TARGET_DEBUG(target, "Target steps one instruction from PC=0x%" PRIx32,
 		buf_get_u32(pc->value, 0, 32));

 	/* the front-end may request us not to handle breakpoints */
@ -2136,7 +2136,7 @@ static int arc_step(struct target *target, int current, target_addr_t address,
 	if (breakpoint)
 		CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));

-	LOG_DEBUG("target stepped ");
+	LOG_TARGET_DEBUG(target, "target stepped");

 	target->state = TARGET_HALTED;

@ -2159,7 +2159,7 @@ static int arc_icache_invalidate(struct target *target)
 	if (!arc->has_icache || arc->icache_invalidated)
 	    return ERROR_OK;

-	LOG_DEBUG("Invalidating I$.");
+	LOG_TARGET_DEBUG(target, "Invalidating I$");

 	value = IC_IVIC_INVALIDATE;	/* invalidate I$ */
 	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
@ -2179,7 +2179,7 @@ static int arc_dcache_invalidate(struct target *target)
 	if (!arc->has_dcache || arc->dcache_invalidated)
 	    return ERROR_OK;

-	LOG_DEBUG("Invalidating D$.");
+	LOG_TARGET_DEBUG(target, "Invalidating D$");

 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
 	dc_ctrl_value = value;
@ -2208,7 +2208,7 @@ static int arc_l2cache_invalidate(struct target *target)
 	if (!arc->has_l2cache || arc->l2cache_invalidated)
 	    return ERROR_OK;

-	LOG_DEBUG("Invalidating L2$.");
+	LOG_TARGET_DEBUG(target, "Invalidating L2$");

 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
 	slc_ctrl_value = value;
@ -2221,7 +2221,7 @@ static int arc_l2cache_invalidate(struct target *target)

 	/* Wait until invalidate operation ends */
 	do {
-	    LOG_DEBUG("Waiting for invalidation end.");
+	    LOG_TARGET_DEBUG(target, "Waiting for invalidation end");
 	    CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
 	} while (value & L2_CTRL_BS);

@ -2259,7 +2259,7 @@ static int arc_dcache_flush(struct target *target)
 	if (!arc->has_dcache || arc->dcache_flushed)
 	    return ERROR_OK;

-	LOG_DEBUG("Flushing D$.");
+	LOG_TARGET_DEBUG(target, "Flushing D$");

 	/* Store current value of DC_CTRL */
 	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
@ -2295,14 +2295,14 @@ static int arc_l2cache_flush(struct target *target)
 	if (!arc->has_l2cache || arc->l2cache_flushed)
 	    return ERROR_OK;

-	LOG_DEBUG("Flushing L2$.");
+	LOG_TARGET_DEBUG(target, "Flushing L2$");

 	/* Flush L2 cache */
 	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));

 	/* Wait until flush operation ends */
 	do {
-	    LOG_DEBUG("Waiting for flushing end.");
+	    LOG_TARGET_DEBUG(target, "Waiting for flushing end");
 	    CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
 	} while (value & L2_CTRL_BS);

--- a/src/target/arc_mem.c
+++ b/src/target/arc_mem.c
@ -35,7 +35,7 @@ static int arc_mem_write_block32(struct target *target, uint32_t addr,
 {
 	struct arc_common *arc = target_to_arc(target);

-	LOG_DEBUG("Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
+	LOG_TARGET_DEBUG(target, "Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
 			addr, count);

 	/* Check arguments */
@ -66,7 +66,7 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
 	uint8_t buffer_te[sizeof(uint32_t)];
 	uint8_t halfword_te[sizeof(uint16_t)];

-	LOG_DEBUG("Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
+	LOG_TARGET_DEBUG(target, "Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
 			addr, count);

 	/* Check arguments */
@ -124,7 +124,7 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
 	uint8_t buffer_te[sizeof(uint32_t)];


-	LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
+	LOG_TARGET_DEBUG(target, "Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
 			addr, count);

 	/* We will read data from memory, so we need to flush the cache. */
@ -158,7 +158,7 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size,
 	int retval = ERROR_OK;
 	void *tunnel = NULL;

-	LOG_DEBUG("address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
+	LOG_TARGET_DEBUG(target, "address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
 		address, size, count);

 	if (target->state != TARGET_HALTED) {
@ -182,7 +182,7 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size,
 		tunnel = calloc(1, count * size * sizeof(uint8_t));

 		if (!tunnel) {
-			LOG_ERROR("Unable to allocate memory");
+			LOG_TARGET_ERROR(target, "Unable to allocate memory");
 			return ERROR_FAIL;
 		}

@ -220,7 +220,7 @@ static int arc_mem_read_block(struct target *target, target_addr_t addr,
 {
 	struct arc_common *arc = target_to_arc(target);

-	LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
+	LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
 			", count=%" PRIu32, addr, size, count);
 	assert(!(addr & 3));
 	assert(size == 4);
@ -243,11 +243,11 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size,
 	uint32_t words_to_read, bytes_to_read;


-	LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
+	LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
 			", count=%" PRIu32, address, size, count);

 	if (target->state != TARGET_HALTED) {
-		LOG_WARNING("target not halted");
+		LOG_TARGET_WARNING(target, "target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}

@ -268,7 +268,7 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size,
 	tunnel_te = calloc(1, bytes_to_read);

 	if (!tunnel_he || !tunnel_te) {
-		LOG_ERROR("Unable to allocate memory");
+		LOG_TARGET_ERROR(target, "Unable to allocate memory");
 		free(tunnel_he);
 		free(tunnel_te);
 		return ERROR_FAIL;
--- a/src/target/arm_cti.c
+++ b/src/target/arm_cti.c
@ -25,7 +25,7 @@ struct arm_cti {
 	struct adiv5_ap *ap;
 };

-static LIST_HEAD(all_cti);
+static OOCD_LIST_HEAD(all_cti);

 const char *arm_cti_name(struct arm_cti *self)
 {
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@ -18,7 +18,7 @@
 #include "transport/transport.h"
 #include "jtag/interface.h"

-static LIST_HEAD(all_dap);
+static OOCD_LIST_HEAD(all_dap);

 extern struct adapter_driver *adapter_driver;

--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@ -126,7 +126,7 @@ struct arm_tpiu_swo_priv_connection {
 	struct arm_tpiu_swo_object *obj;
 };

-static LIST_HEAD(all_tpiu_swo);
+static OOCD_LIST_HEAD(all_tpiu_swo);

 #define ARM_TPIU_SWO_TRACE_BUF_SIZE	4096

--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@ -248,7 +248,11 @@ enum arm_mode armv4_5_number_to_mode(int number)
 }

 static const char *arm_state_strings[] = {
-	"ARM", "Thumb", "Jazelle", "ThumbEE",
+	[ARM_STATE_ARM]      = "ARM",
+	[ARM_STATE_THUMB]    = "Thumb",
+	[ARM_STATE_JAZELLE]  = "Jazelle",
+	[ARM_STATE_THUMB_EE] = "ThumbEE",
+	[ARM_STATE_AARCH64]  = "AArch64",
 };

 /* Templates for ARM core registers.
@ -430,6 +434,16 @@ const int armv4_5_core_reg_map[9][17] = {
 	}
 };

+static const char *arm_core_state_string(struct arm *arm)
+{
+	if (arm->core_state > ARRAY_SIZE(arm_state_strings)) {
+		LOG_ERROR("core_state exceeds table size");
+		return "Unknown";
+	}
+
+	return arm_state_strings[arm->core_state];
+}
+
 /**
 * Configures host-side ARM records to reflect the specified CPSR.
 * Later, code can use arm_reg_current() to map register numbers
@ -484,7 +498,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)

 	LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
 		arm_mode_name(mode),
-		arm_state_strings[arm->core_state]);
+		arm_core_state_string(arm));
 }

 /**
@ -794,7 +808,7 @@ int arm_arch_state(struct target *target)

 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 		"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
-		arm_state_strings[arm->core_state],
+		arm_core_state_string(arm),
 		debug_reason_name(target),
 		arm_mode_name(arm->core_mode),
 		buf_get_u32(arm->cpsr->value, 0, 32),
@ -929,7 +943,7 @@ COMMAND_HANDLER(handle_arm_core_state_command)
 			arm->core_state = ARM_STATE_THUMB;
 	}

-	command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
+	command_print(CMD, "core state: %s", arm_core_state_string(arm));

 	return ret;
 }
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@ -171,7 +171,7 @@ int armv7m_restore_context(struct target *target)
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct reg_cache *cache = armv7m->arm.core_cache;

-	LOG_DEBUG(" ");
+	LOG_TARGET_DEBUG(target, " ");

 	if (armv7m->pre_restore_context)
 		armv7m->pre_restore_context(target);
@ -366,9 +366,9 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
 			buf_set_u32(r->value + 4, 0, 32, reg_value);

 			uint64_t q = buf_get_u64(r->value, 0, 64);
-			LOG_DEBUG("read %s value 0x%016" PRIx64, r->name, q);
+			LOG_TARGET_DEBUG(target, "read %s value 0x%016" PRIx64, r->name, q);
 		} else {
-			LOG_DEBUG("read %s value 0x%08" PRIx32, r->name, reg_value);
+			LOG_TARGET_DEBUG(target, "read %s value 0x%08" PRIx32, r->name, reg_value);
 		}
 	}

@ -436,9 +436,9 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
 				goto out_error;

 			uint64_t q = buf_get_u64(value, 0, 64);
-			LOG_DEBUG("write %s value 0x%016" PRIx64, r->name, q);
+			LOG_TARGET_DEBUG(target, "write %s value 0x%016" PRIx64, r->name, q);
 		} else {
-			LOG_DEBUG("write %s value 0x%08" PRIx32, r->name, t);
+			LOG_TARGET_DEBUG(target, "write %s value 0x%08" PRIx32, r->name, t);
 		}
 	}

@ -449,7 +449,7 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,

 out_error:
 	r->dirty = true;
-	LOG_ERROR("Error setting register %s", r->name);
+	LOG_TARGET_ERROR(target, "Error setting register %s", r->name);
 	return retval;
 }

@ -520,7 +520,7 @@ int armv7m_start_algorithm(struct target *target,
 	 * at the exit point */

 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
-		LOG_ERROR("current target isn't an ARMV7M target");
+		LOG_TARGET_ERROR(target, "current target isn't an ARMV7M target");
 		return ERROR_TARGET_INVALID;
 	}

@ -563,12 +563,12 @@ int armv7m_start_algorithm(struct target *target,
 /*		uint32_t regvalue; */

 		if (!reg) {
-			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+			LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}

 		if (reg->size != reg_params[i].size) {
-			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+			LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size",
 				reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
@ -600,10 +600,11 @@ int armv7m_start_algorithm(struct target *target,
 		/* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
 		if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
 			armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
-			LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
+			LOG_TARGET_INFO(target, "ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
 		}

-		LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+		LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x",
+			armv7m_algorithm_info->core_mode);
 		buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 			0, 1, armv7m_algorithm_info->core_mode);
 		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
@ -633,7 +634,7 @@ int armv7m_wait_algorithm(struct target *target,
 	 * at the exit point */

 	if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
-		LOG_ERROR("current target isn't an ARMV7M target");
+		LOG_TARGET_ERROR(target, "current target isn't an ARMV7M target");
 		return ERROR_TARGET_INVALID;
 	}

@ -653,7 +654,7 @@ int armv7m_wait_algorithm(struct target *target,
 		/* PC value has been cached in cortex_m_debug_entry() */
 		uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
 		if (pc != exit_point) {
-			LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
+			LOG_TARGET_DEBUG(target, "failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
 					  pc, exit_point);
 			return ERROR_TARGET_ALGO_EXIT;
 		}
@ -678,12 +679,13 @@ int armv7m_wait_algorithm(struct target *target,
 					false);

 			if (!reg) {
-				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+				LOG_TARGET_ERROR(target, "BUG: register '%s' not found",
+					reg_params[i].reg_name);
 				return ERROR_COMMAND_SYNTAX_ERROR;
 			}

 			if (reg->size != reg_params[i].size) {
-				LOG_ERROR(
+				LOG_TARGET_ERROR(target,
 					"BUG: register '%s' size doesn't match reg_params[i].size",
 					reg_params[i].reg_name);
 				return ERROR_COMMAND_SYNTAX_ERROR;
@ -701,7 +703,7 @@ int armv7m_wait_algorithm(struct target *target,
 		uint32_t regvalue;
 		regvalue = buf_get_u32(reg->value, 0, 32);
 		if (regvalue != armv7m_algorithm_info->context[i]) {
-			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
+			LOG_TARGET_DEBUG(target, "restoring register %s with value 0x%8.8" PRIx32,
 					  reg->name, armv7m_algorithm_info->context[i]);
 			buf_set_u32(reg->value,
 				0, 32, armv7m_algorithm_info->context[i]);
@ -712,7 +714,7 @@ int armv7m_wait_algorithm(struct target *target,

 	/* restore previous core mode */
 	if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
-		LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+		LOG_TARGET_DEBUG(target, "restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 		buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 			0, 1, armv7m_algorithm_info->core_mode);
 		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
@ -738,9 +740,8 @@ int armv7m_arch_state(struct target *target)
 	ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 	sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);

-	LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
+	LOG_TARGET_USER(target, "halted due to %s, current mode: %s %s\n"
 		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
-		target_name(target),
 		debug_reason_name(target),
 		arm_mode_name(arm->core_mode),
 		armv7m_exception_string(armv7m->exception_number),
@ -807,13 +808,13 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
 			feature->name = armv7m_regs[i].feature;
 			reg_list[i].feature = feature;
 		} else
-			LOG_ERROR("unable to allocate feature list");
+			LOG_TARGET_ERROR(target, "unable to allocate feature list");

 		reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
 		if (reg_list[i].reg_data_type)
 			reg_list[i].reg_data_type->type = armv7m_regs[i].type;
 		else
-			LOG_ERROR("unable to allocate reg type list");
+			LOG_TARGET_ERROR(target, "unable to allocate reg type list");
 	}

 	arm->cpsr = reg_list + ARMV7M_XPSR;
@ -918,7 +919,7 @@ int armv7m_checksum_memory(struct target *target,
 	if (retval == ERROR_OK)
 		*checksum = buf_get_u32(reg_params[0].value, 0, 32);
 	else
-		LOG_ERROR("error executing cortex_m crc algorithm");
+		LOG_TARGET_ERROR(target, "error executing cortex_m crc algorithm");

 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
@ -1003,7 +1004,7 @@ int armv7m_blank_check_memory(struct target *target,
 	uint32_t erased_word = erased_value | (erased_value << 8)
 			       | (erased_value << 16) | (erased_value << 24);

-	LOG_DEBUG("Starting erase check of %d blocks, parameters@"
+	LOG_TARGET_DEBUG(target, "Starting erase check of %d blocks, parameters@"
 		 TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);

 	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
@ -1044,7 +1045,8 @@ int armv7m_blank_check_memory(struct target *target,
 		blocks[i].result = result;
 	}
 	if (i && timed_out)
-		LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
+		LOG_TARGET_INFO(target, "Slow CPU clock: %d blocks checked, %d remain. Continuing...",
+			i, num_blocks - i);

 	retval = i;		/* return number of blocks really checked */

@ -1085,7 +1087,7 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 				r->dirty = true;
 				r->valid = true;
 				result = true;
-				LOG_DEBUG("Skipping over BKPT instruction");
+				LOG_TARGET_DEBUG(target, "Skipping over BKPT instruction");
 			}
 		}
 	}
--- a/src/target/esirisc.c
+++ b/src/target/esirisc.c
@ -160,11 +160,11 @@ static int esirisc_disable_interrupts(struct target *target)
 	uint32_t etc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC");
 		return retval;
 	}

@ -172,7 +172,7 @@ static int esirisc_disable_interrupts(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC");
 		return retval;
 	}

@ -187,11 +187,11 @@ static int esirisc_enable_interrupts(struct target *target)
 	uint32_t etc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC");
 		return retval;
 	}

@ -199,7 +199,7 @@ static int esirisc_enable_interrupts(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC");
 		return retval;
 	}

@ -212,12 +212,12 @@ static int esirisc_save_interrupts(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
 			&esirisc->etc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETC");
 		return retval;
 	}

@ -229,12 +229,12 @@ static int esirisc_restore_interrupts(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
 			esirisc->etc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: ETC");
 		return retval;
 	}

@ -247,12 +247,12 @@ static int esirisc_save_hwdc(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
 			&esirisc->hwdc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: HWDC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: HWDC");
 		return retval;
 	}

@ -265,12 +265,12 @@ static int esirisc_restore_hwdc(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
 			esirisc->hwdc_save);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: HWDC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: HWDC");
 		return retval;
 	}

@ -281,7 +281,7 @@ static int esirisc_save_context(struct target *target)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 		struct reg *reg = esirisc->reg_cache->reg_list + i;
@ -298,7 +298,7 @@ static int esirisc_restore_context(struct target *target)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 		struct reg *reg = esirisc->reg_cache->reg_list + i;
@ -316,7 +316,7 @@ static int esirisc_flush_caches(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
@ -325,7 +325,7 @@ static int esirisc_flush_caches(struct target *target)

 	int retval = esirisc_jtag_flush_caches(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to flush caches", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to flush caches");
 		return retval;
 	}

@ -337,7 +337,7 @@ static int esirisc_wait_debug_active(struct esirisc_common *esirisc, int ms)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int64_t t;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(esirisc->target, "-");

 	t = timeval_ms();
 	for (;;) {
@ -359,7 +359,7 @@ static int esirisc_read_memory(struct target *target, target_addr_t address,
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int num_bits = 8 * size;
 	for (uint32_t i = 0; i < count; ++i) {
@ -383,12 +383,12 @@ static int esirisc_read_memory(struct target *target, target_addr_t address,
 				break;

 			default:
-				LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
+				LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size);
 				return ERROR_FAIL;
 		}

 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
+			LOG_TARGET_ERROR(target, "failed to read address: 0x%" TARGET_PRIxADDR,
 					address);
 			return retval;
 		}
@ -408,7 +408,7 @@ static int esirisc_write_memory(struct target *target, target_addr_t address,
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int num_bits = 8 * size;
 	for (uint32_t i = 0; i < count; ++i) {
@ -431,12 +431,12 @@ static int esirisc_write_memory(struct target *target, target_addr_t address,
 				break;

 			default:
-				LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
+				LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size);
 				return ERROR_FAIL;
 		}

 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR, target_name(target),
+			LOG_TARGET_ERROR(target, "failed to write address: 0x%" TARGET_PRIxADDR,
 					address);
 			return retval;
 		}
@ -460,7 +460,7 @@ static int esirisc_next_breakpoint(struct target *target)
 	struct breakpoint **breakpoints_p = esirisc->breakpoints_p;
 	struct breakpoint **breakpoints_e = breakpoints_p + esirisc->num_breakpoints;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	for (int bp_index = 0; breakpoints_p < breakpoints_e; ++breakpoints_p, ++bp_index)
 		if (!*breakpoints_p)
@ -477,7 +477,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea
 	uint32_t ibc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/*
 	 * The default linker scripts provided by the eSi-RISC toolchain do
@ -491,7 +491,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea

 	bp_index = esirisc_next_breakpoint(target);
 	if (bp_index < 0) {
-		LOG_ERROR("%s: out of hardware breakpoints", target_name(target));
+		LOG_TARGET_ERROR(target, "out of hardware breakpoints");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}

@ -502,14 +502,14 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBA_N + bp_index,
 			breakpoint->address);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBA");
 		return retval;
 	}

 	/* enable instruction breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: IBC");
 		return retval;
 	}

@ -517,7 +517,7 @@ static int esirisc_add_breakpoint(struct target *target, struct breakpoint *brea

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC");
 		return retval;
 	}

@ -528,7 +528,7 @@ static int esirisc_add_breakpoints(struct target *target)
 {
 	struct breakpoint *breakpoint = target->breakpoints;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	while (breakpoint) {
 		if (!breakpoint->is_set)
@ -548,12 +548,12 @@ static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *b
 	uint32_t ibc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/* disable instruction breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: IBC");
 		return retval;
 	}

@ -561,7 +561,7 @@ static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *b

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC");
 		return retval;
 	}

@ -576,12 +576,12 @@ static int esirisc_remove_breakpoints(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/* clear instruction breakpoints */
 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, 0);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: IBC");
 		return retval;
 	}

@ -596,7 +596,7 @@ static int esirisc_next_watchpoint(struct target *target)
 	struct watchpoint **watchpoints_p = esirisc->watchpoints_p;
 	struct watchpoint **watchpoints_e = watchpoints_p + esirisc->num_watchpoints;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	for (int wp_index = 0; watchpoints_p < watchpoints_e; ++watchpoints_p, ++wp_index)
 		if (!*watchpoints_p)
@ -613,11 +613,11 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 	uint32_t dbs, dbc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	wp_index = esirisc_next_watchpoint(target);
 	if (wp_index < 0) {
-		LOG_ERROR("%s: out of hardware watchpoints", target_name(target));
+		LOG_TARGET_ERROR(target, "out of hardware watchpoints");
 		return ERROR_FAIL;
 	}

@ -628,14 +628,14 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBA_N + wp_index,
 			watchpoint->address);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBA");
 		return retval;
 	}

 	/* specify data breakpoint size */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, &dbs);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DBS", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBS");
 		return retval;
 	}

@ -657,7 +657,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 			break;

 		default:
-			LOG_ERROR("%s: unsupported length: %" PRIu32, target_name(target),
+			LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32,
 					watchpoint->length);
 			return ERROR_FAIL;
 	}
@ -666,14 +666,14 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, dbs);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBS", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBS");
 		return retval;
 	}

 	/* enable data breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBC");
 		return retval;
 	}

@ -692,8 +692,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
 			break;

 		default:
-			LOG_ERROR("%s: unsupported rw: %" PRId32, target_name(target),
-					watchpoint->rw);
+			LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw);
 			return ERROR_FAIL;
 	}

@ -701,7 +700,7 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC");
 		return retval;
 	}

@ -712,7 +711,7 @@ static int esirisc_add_watchpoints(struct target *target)
 {
 	struct watchpoint *watchpoint = target->watchpoints;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	while (watchpoint) {
 		if (!watchpoint->is_set)
@ -732,12 +731,12 @@ static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *w
 	uint32_t dbc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/* disable data breakpoint */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DBC");
 		return retval;
 	}

@ -745,7 +744,7 @@ static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *w

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC");
 		return retval;
 	}

@ -760,12 +759,12 @@ static int esirisc_remove_watchpoints(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/* clear data breakpoints */
 	int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, 0);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DBC");
 		return retval;
 	}

@ -779,14 +778,14 @@ static int esirisc_halt(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (target->state == TARGET_HALTED)
 		return ERROR_OK;

 	int retval = esirisc_jtag_break(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to halt target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to halt target");
 		return retval;
 	}

@ -802,11 +801,11 @@ static int esirisc_disable_step(struct target *target)
 	uint32_t dc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DC");
 		return retval;
 	}

@ -814,7 +813,7 @@ static int esirisc_disable_step(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DC");
 		return retval;
 	}

@ -828,11 +827,11 @@ static int esirisc_enable_step(struct target *target)
 	uint32_t dc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Debug CSR: DC");
 		return retval;
 	}

@ -840,7 +839,7 @@ static int esirisc_enable_step(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Debug CSR: DC");
 		return retval;
 	}

@ -855,7 +854,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
 	struct breakpoint *breakpoint = NULL;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
@ -901,7 +900,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add

 	retval = esirisc_jtag_continue(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to resume target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to resume target");
 		return retval;
 	}

@ -921,7 +920,7 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
 static int esirisc_resume(struct target *target, int current, target_addr_t address,
 		int handle_breakpoints, int debug_execution)
 {
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	return esirisc_resume_or_step(target, current, address,
 			handle_breakpoints, debug_execution, false);
@ -930,7 +929,7 @@ static int esirisc_resume(struct target *target, int current, target_addr_t addr
 static int esirisc_step(struct target *target, int current, target_addr_t address,
 		int handle_breakpoints)
 {
-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	return esirisc_resume_or_step(target, current, address,
 			handle_breakpoints, 0, true);
@ -942,20 +941,20 @@ static int esirisc_debug_step(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	esirisc_disable_interrupts(target);
 	esirisc_enable_step(target);

 	retval = esirisc_jtag_continue(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to resume target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to resume target");
 		return retval;
 	}

 	retval = esirisc_wait_debug_active(esirisc, STEP_TIMEOUT);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: step timed out", target_name(target));
+		LOG_TARGET_ERROR(target, "step timed out");
 		return retval;
 	}

@ -971,23 +970,23 @@ static int esirisc_debug_reset(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_assert_reset(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to assert reset", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to assert reset");
 		return retval;
 	}

 	retval = esirisc_jtag_deassert_reset(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to deassert reset", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to deassert reset");
 		return retval;
 	}

 	retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: reset timed out", target_name(target));
+		LOG_TARGET_ERROR(target, "reset timed out");
 		return retval;
 	}

@ -1000,11 +999,11 @@ static int esirisc_debug_enable(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_enable_debug(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to enable debug mode", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to enable debug mode");
 		return retval;
 	}

@ -1015,13 +1014,13 @@ static int esirisc_debug_enable(struct target *target)
 	 * targets, which will respond with all ones and appear active.
 	 */
 	if (esirisc_jtag_is_stopped(jtag_info)) {
-		LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target));
+		LOG_TARGET_INFO(target, "debug clock inactive; attempting debug reset");
 		retval = esirisc_debug_reset(target);
 		if (retval != ERROR_OK)
 			return retval;

 		if (esirisc_jtag_is_stopped(jtag_info)) {
-			LOG_ERROR("%s: target unresponsive; giving up", target_name(target));
+			LOG_TARGET_ERROR(target, "target unresponsive; giving up");
 			return ERROR_FAIL;
 		}
 	}
@ -1034,7 +1033,7 @@ static int esirisc_debug_entry(struct target *target)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct breakpoint *breakpoint;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	esirisc_save_context(target);

@ -1087,12 +1086,12 @@ static int esirisc_poll(struct target *target)

 	retval = esirisc_jtag_enable_debug(jtag_info);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to poll target", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to poll target");
 		return retval;
 	}

 	if (esirisc_jtag_is_stopped(jtag_info)) {
-		LOG_ERROR("%s: target has stopped; reset required", target_name(target));
+		LOG_TARGET_ERROR(target, "target has stopped; reset required");
 		target->state = TARGET_UNKNOWN;
 		return ERROR_TARGET_FAILURE;
 	}
@ -1122,7 +1121,7 @@ static int esirisc_assert_reset(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (jtag_get_reset_config() & RESET_HAS_SRST) {
 		jtag_add_reset(1, 1);
@ -1134,7 +1133,7 @@ static int esirisc_assert_reset(struct target *target)

 		retval = esirisc_jtag_assert_reset(jtag_info);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to assert reset", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to assert reset");
 			return retval;
 		}
 	}
@ -1153,19 +1152,19 @@ static int esirisc_reset_entry(struct target *target)
 	uint32_t eta, epc;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/* read exception table address */
 	retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETA, &eta);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Thread CSR: ETA", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Thread CSR: ETA");
 		return retval;
 	}

 	/* read reset entry point */
 	retval = esirisc_jtag_read_word(jtag_info, eta + ENTRY_RESET, &epc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
+		LOG_TARGET_ERROR(target, "failed to read address: 0x%" TARGET_PRIxADDR,
 				(target_addr_t)epc);
 		return retval;
 	}
@ -1173,7 +1172,7 @@ static int esirisc_reset_entry(struct target *target)
 	/* write reset entry point */
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_EPC, epc);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Thread CSR: EPC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Thread CSR: EPC");
 		return retval;
 	}

@ -1186,7 +1185,7 @@ static int esirisc_deassert_reset(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (jtag_get_reset_config() & RESET_HAS_SRST) {
 		jtag_add_reset(0, 0);
@ -1202,14 +1201,14 @@ static int esirisc_deassert_reset(struct target *target)
 	} else {
 		retval = esirisc_jtag_deassert_reset(jtag_info);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to deassert reset", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to deassert reset");
 			return retval;
 		}
 	}

 	retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: reset timed out", target_name(target));
+		LOG_TARGET_ERROR(target, "reset timed out");
 		return retval;
 	}

@ -1225,7 +1224,7 @@ static int esirisc_deassert_reset(struct target *target)
 	if (!target->reset_halt) {
 		retval = esirisc_jtag_continue(jtag_info);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to resume target", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to resume target");
 			return retval;
 		}
 	}
@ -1241,7 +1240,7 @@ static int esirisc_arch_state(struct target *target)
 	uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
 	uint32_t ed = buf_get_u32(esirisc->ed->value, 0, esirisc->ed->size);

-	LOG_USER("target halted due to %s, exception: %s\n"
+	LOG_TARGET_USER(target, "target halted due to %s, exception: %s\n"
 			"EPC: 0x%" PRIx32 ", ECAS: 0x%" PRIx32 ", EID: 0x%" PRIx32 ", ED: 0x%" PRIx32,
 			debug_reason_name(target), esirisc_exception_strings[eid], epc, ecas, eid, ed);

@ -1252,7 +1251,7 @@ static const char *esirisc_get_gdb_arch(const struct target *target)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	/*
 	 * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a
@ -1272,7 +1271,7 @@ static int esirisc_get_gdb_reg_list(struct target *target, struct reg **reg_list
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	*reg_list_size = ESIRISC_NUM_REGS;

@ -1302,11 +1301,11 @@ static int esirisc_read_reg(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_read_reg(jtag_info, reg->number, &data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read register: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to read register: %s", reg->name);
 		return retval;
 	}

@ -1325,11 +1324,11 @@ static int esirisc_write_reg(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data = buf_get_u32(reg->value, 0, reg->size);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_write_reg(jtag_info, reg->number, data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write register: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to write register: %s", reg->name);
 		return retval;
 	}

@ -1347,11 +1346,11 @@ static int esirisc_read_csr(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_read_csr(jtag_info, reg_info->bank, reg_info->csr, &data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read CSR: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to read CSR: %s", reg->name);
 		return retval;
 	}

@ -1370,11 +1369,11 @@ static int esirisc_write_csr(struct reg *reg)
 	struct target *target = esirisc->target;
 	uint32_t data = buf_get_u32(reg->value, 0, reg->size);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	int retval = esirisc_jtag_write_csr(jtag_info, reg_info->bank, reg_info->csr, data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write CSR: %s", target_name(target), reg->name);
+		LOG_TARGET_ERROR(target, "failed to write CSR: %s", reg->name);
 		return retval;
 	}

@ -1390,7 +1389,7 @@ static int esirisc_get_reg(struct reg *reg)
 	struct esirisc_common *esirisc = reg_info->esirisc;
 	struct target *target = esirisc->target;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (target->state != TARGET_HALTED)
 		return ERROR_TARGET_NOT_HALTED;
@ -1405,7 +1404,7 @@ static int esirisc_set_reg(struct reg *reg, uint8_t *buf)
 	struct target *target = esirisc->target;
 	uint32_t value = buf_get_u32(buf, 0, reg->size);

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (target->state != TARGET_HALTED)
 		return ERROR_TARGET_NOT_HALTED;
@ -1429,7 +1428,7 @@ static struct reg_cache *esirisc_build_reg_cache(struct target *target)
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 	struct reg *reg_list = calloc(ESIRISC_NUM_REGS, sizeof(struct reg));

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	cache->name = "eSi-RISC registers";
 	cache->next = NULL;
@ -1519,11 +1518,11 @@ static int esirisc_identify(struct target *target)
 	uint32_t csr;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_ARCH0, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: ARCH0", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: ARCH0");
 		return retval;
 	}

@ -1532,7 +1531,7 @@ static int esirisc_identify(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_MEM, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: MEM", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: MEM");
 		return retval;
 	}

@ -1541,7 +1540,7 @@ static int esirisc_identify(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_IC, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: IC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: IC");
 		return retval;
 	}

@ -1549,7 +1548,7 @@ static int esirisc_identify(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DC, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: DC", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: DC");
 		return retval;
 	}

@ -1557,7 +1556,7 @@ static int esirisc_identify(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DBG, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: DBG", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: DBG");
 		return retval;
 	}

@ -1566,7 +1565,7 @@ static int esirisc_identify(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_TRACE, &csr);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Configuration CSR: TRACE", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Configuration CSR: TRACE");
 		return retval;
 	}

@ -1584,8 +1583,7 @@ static int esirisc_target_create(struct target *target, Jim_Interp *interp)
 		return ERROR_FAIL;

 	if (tap->ir_length != INSTR_LENGTH) {
-		LOG_ERROR("%s: invalid IR length; expected %d", target_name(target),
-				INSTR_LENGTH);
+		LOG_TARGET_ERROR(target, "invalid IR length; expected %d", INSTR_LENGTH);
 		return ERROR_FAIL;
 	}

@ -1629,7 +1627,7 @@ static int esirisc_examine(struct target *target)
 	struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 	int retval;

-	LOG_DEBUG("-");
+	LOG_TARGET_DEBUG(target, "-");

 	if (!target_was_examined(target)) {
 		retval = esirisc_debug_enable(target);
@ -1649,7 +1647,7 @@ static int esirisc_examine(struct target *target)
 		} else {
 			retval = esirisc_jtag_break(jtag_info);
 			if (retval != ERROR_OK) {
-				LOG_ERROR("%s: failed to halt target", target_name(target));
+				LOG_TARGET_ERROR(target, "failed to halt target");
 				return retval;
 			}

@ -1658,7 +1656,7 @@ static int esirisc_examine(struct target *target)

 		retval = esirisc_identify(target);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("%s: failed to identify target", target_name(target));
+			LOG_TARGET_ERROR(target, "failed to identify target");
 			return retval;
 		}

@ -1675,20 +1673,20 @@ static int esirisc_examine(struct target *target)
 		else {
 			retval = esirisc_jtag_continue(jtag_info);
 			if (retval != ERROR_OK) {
-				LOG_ERROR("%s: failed to resume target", target_name(target));
+				LOG_TARGET_ERROR(target, "failed to resume target");
 				return retval;
 			}
 		}

 		target_set_examined(target);

-		LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target),
+		LOG_TARGET_INFO(target, "%d bit, %d registers, %s%s%s",
 				esirisc->num_bits, esirisc->num_regs,
 				target_endianness(target),
 				esirisc->has_icache ? ", icache" : "",
 				esirisc->has_dcache ? ", dcache" : "");

-		LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints%s", target_name(target),
+		LOG_TARGET_INFO(target, "hardware has %d breakpoints, %d watchpoints%s",
 				esirisc->num_breakpoints, esirisc->num_watchpoints,
 				esirisc->has_trace ? ", trace" : "");
 	}
@ -1707,7 +1705,7 @@ COMMAND_HANDLER(handle_esirisc_cache_arch_command)
 		else if (strcmp(*CMD_ARGV, "von_neumann") == 0)
 			esirisc->cache_arch = ESIRISC_CACHE_VON_NEUMANN;
 		else {
-			LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV);
+			LOG_TARGET_ERROR(target, "invalid cache_arch: %s", *CMD_ARGV);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 	}
@ -1724,7 +1722,7 @@ COMMAND_HANDLER(handle_esirisc_flush_caches_command)
 	int retval;

 	if (!esirisc_has_cache(esirisc)) {
-		LOG_ERROR("target does not support caching");
+		LOG_TARGET_ERROR(target, "target does not support caching");
 		return ERROR_FAIL;
 	}

@ -1770,7 +1768,7 @@ COMMAND_HANDLER(handle_esirisc_hwdc_command)
 				while (CMD_ARGC-- > 0) {
 					int mask = esirisc_find_hwdc_mask(CMD_ARGV[CMD_ARGC]);
 					if (mask < 0) {
-						LOG_ERROR("invalid mask: %s", CMD_ARGV[CMD_ARGC]);
+						LOG_TARGET_ERROR(target, "invalid mask: %s", CMD_ARGV[CMD_ARGC]);
 						return ERROR_COMMAND_SYNTAX_ERROR;
 					}
 					esirisc->hwdc_save |= mask;
--- a/src/target/esirisc_trace.c
+++ b/src/target/esirisc_trace.c
@ -85,7 +85,7 @@ static int esirisc_trace_clear_status(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STATUS, ~0);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Status", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Status");
 		return retval;
 	}

@ -102,7 +102,7 @@ static int esirisc_trace_get_status(struct target *target, uint32_t *status)

 	int retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_STATUS, status);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: Status", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: Status");
 		return retval;
 	}

@ -121,7 +121,7 @@ static int esirisc_trace_start(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, &control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: Control");
 		return retval;
 	}

@ -129,7 +129,7 @@ static int esirisc_trace_start(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control");
 		return retval;
 	}

@ -148,7 +148,7 @@ static int esirisc_trace_stop(struct target *target)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, &control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: Control");
 		return retval;
 	}

@ -156,7 +156,7 @@ static int esirisc_trace_stop(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control");
 		return retval;
 	}

@ -195,7 +195,7 @@ static int esirisc_trace_init(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_CONTROL, control);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Control", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Control");
 		return retval;
 	}

@ -203,14 +203,14 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_START,
 			trace_info->buffer_start);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: BufferStart", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferStart");
 		return retval;
 	}

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_END,
 			trace_info->buffer_end);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: BufferEnd", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferEnd");
 		return retval;
 	}

@ -221,7 +221,7 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_CUR,
 			trace_info->buffer_start);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: BufferCurrent", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: BufferCurrent");
 		return retval;
 	}

@ -241,7 +241,7 @@ static int esirisc_trace_init(struct target *target)

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_TRIGGER, trigger);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Trigger", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Trigger");
 		return retval;
 	}

@ -249,14 +249,14 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_START_DATA,
 			trace_info->start_data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StartData", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StartData");
 		return retval;
 	}

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_START_MASK,
 			trace_info->start_mask);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StartMask", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StartMask");
 		return retval;
 	}

@ -264,14 +264,14 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STOP_DATA,
 			trace_info->stop_data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StopData", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StopData");
 		return retval;
 	}

 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_STOP_MASK,
 			trace_info->stop_mask);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: StopMask", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: StopMask");
 		return retval;
 	}

@ -279,7 +279,7 @@ static int esirisc_trace_init(struct target *target)
 	retval = esirisc_jtag_write_csr(jtag_info, CSR_TRACE, CSR_TRACE_DELAY,
 			trace_info->delay_cycles);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to write Trace CSR: Delay", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to write Trace CSR: Delay");
 		return retval;
 	}

@ -326,7 +326,7 @@ static int esirisc_trace_read_memory(struct target *target, target_addr_t addres

 	retval = target_read_memory(target, address, 1, size, buffer);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read trace data", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read trace data");
 		return retval;
 	}

@ -346,7 +346,7 @@ static int esirisc_trace_read_buffer(struct target *target, uint8_t *buffer)

 	retval = esirisc_jtag_read_csr(jtag_info, CSR_TRACE, CSR_TRACE_BUFFER_CUR, &buffer_cur);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("%s: failed to read Trace CSR: BufferCurrent", target_name(target));
+		LOG_TARGET_ERROR(target, "failed to read Trace CSR: BufferCurrent");
 		return retval;
 	}

--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@ -34,13 +34,13 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
 		return ERROR_FAIL;

 	if (pc->ap_num == DP_APSEL_INVALID) {
-		LOG_ERROR("AP number not specified");
+		LOG_TARGET_ERROR(target, "AP number not specified");
 		return ERROR_FAIL;
 	}

 	mem_ap = calloc(1, sizeof(struct mem_ap));
 	if (!mem_ap) {
-		LOG_ERROR("Out of memory");
+		LOG_TARGET_ERROR(target, "Out of memory");
 		return ERROR_FAIL;
 	}

@ -58,7 +58,7 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp)

 static int mem_ap_init_target(struct command_context *cmd_ctx, struct target *target)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_UNKNOWN;
 	target->debug_reason = DBG_REASON_UNDEFINED;
 	return ERROR_OK;
@ -68,7 +68,7 @@ static void mem_ap_deinit_target(struct target *target)
 {
 	struct mem_ap *mem_ap = target->arch_info;

-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);

 	if (mem_ap->ap)
 		dap_put_ap(mem_ap->ap);
@ -79,7 +79,7 @@ static void mem_ap_deinit_target(struct target *target)

 static int mem_ap_arch_state(struct target *target)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	return ERROR_OK;
 }

@ -95,7 +95,7 @@ static int mem_ap_poll(struct target *target)

 static int mem_ap_halt(struct target *target)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_HALTED;
 	target->debug_reason = DBG_REASON_DBGRQ;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@ -105,7 +105,7 @@ static int mem_ap_halt(struct target *target)
 static int mem_ap_resume(struct target *target, int current, target_addr_t address,
 		int handle_breakpoints, int debug_execution)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_RUNNING;
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	return ERROR_OK;
@ -114,7 +114,7 @@ static int mem_ap_resume(struct target *target, int current, target_addr_t addre
 static int mem_ap_step(struct target *target, int current, target_addr_t address,
 				int handle_breakpoints)
 {
-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	target->state = TARGET_HALTED;
 	target->debug_reason = DBG_REASON_DBGRQ;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@ -126,7 +126,7 @@ static int mem_ap_assert_reset(struct target *target)
 	target->state = TARGET_RESET;
 	target->debug_reason = DBG_REASON_UNDEFINED;

-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	return ERROR_OK;
 }

@ -138,7 +138,7 @@ static int mem_ap_examine(struct target *target)
 		if (!mem_ap->ap) {
 			mem_ap->ap = dap_get_ap(mem_ap->dap, mem_ap->ap_num);
 			if (!mem_ap->ap) {
-				LOG_ERROR("Cannot get AP");
+				LOG_TARGET_ERROR(target, "Cannot get AP");
 				return ERROR_FAIL;
 			}
 		}
@ -162,7 +162,7 @@ static int mem_ap_deassert_reset(struct target *target)
 		target->debug_reason = DBG_REASON_NOTHALTED;
 	}

-	LOG_DEBUG("%s", __func__);
+	LOG_TARGET_DEBUG(target, "%s", __func__);
 	return ERROR_OK;
 }

@ -212,7 +212,7 @@ static int mem_ap_get_gdb_reg_list(struct target *target, struct reg **reg_list[
 {
 	struct mem_ap_alloc_reg_list *mem_ap_alloc = calloc(1, sizeof(struct mem_ap_alloc_reg_list));
 	if (!mem_ap_alloc) {
-		LOG_ERROR("Out of memory");
+		LOG_TARGET_ERROR(target, "Out of memory");
 		return ERROR_FAIL;
 	}

@ -237,7 +237,7 @@ static int mem_ap_read_memory(struct target *target, target_addr_t address,
 {
 	struct mem_ap *mem_ap = target->arch_info;

-	LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
+	LOG_TARGET_DEBUG(target, "Reading memory at physical address " TARGET_ADDR_FMT
 		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);

 	if (count == 0 || !buffer)
@ -252,7 +252,7 @@ static int mem_ap_write_memory(struct target *target, target_addr_t address,
 {
 	struct mem_ap *mem_ap = target->arch_info;

-	LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
+	LOG_TARGET_DEBUG(target, "Writing memory at physical address " TARGET_ADDR_FMT
 		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);

 	if (count == 0 || !buffer)
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@ -400,7 +400,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in
 		ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
 		uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
 		if (!(ejtag_ctrl & EJTAG_CTRL_PRACC)) {
-			LOG_ERROR("Error: access not pending  count: %d", scan_count);
+			LOG_ERROR("Access not pending, count: %d", scan_count);
 			retval = ERROR_FAIL;
 			goto exit;
 		}
--- a/src/target/mips64_pracc.c
+++ b/src/target/mips64_pracc.c
@ -76,12 +76,12 @@ static int mips64_pracc_exec_read(struct mips64_pracc_context *ctx, uint64_t add
 		offset = (address - MIPS64_PRACC_PARAM_IN) / MIPS64_PRACC_DATA_STEP;

 		if (offset >= MIPS64_PRACC_PARAM_IN_SIZE) {
-			LOG_ERROR("Error: iparam size exceeds MIPS64_PRACC_PARAM_IN_SIZE");
+			LOG_ERROR("iparam size exceeds MIPS64_PRACC_PARAM_IN_SIZE");
 			return ERROR_JTAG_DEVICE_ERROR;
 		}

 		if (!ctx->local_iparam) {
-			LOG_ERROR("Error: unexpected reading of input parameter");
+			LOG_ERROR("unexpected reading of input parameter");
 			return ERROR_JTAG_DEVICE_ERROR;
 		}

@ -93,7 +93,7 @@ static int mips64_pracc_exec_read(struct mips64_pracc_context *ctx, uint64_t add

 		offset = (address - MIPS64_PRACC_PARAM_OUT) / MIPS64_PRACC_DATA_STEP;
 		if (!ctx->local_oparam) {
-			LOG_ERROR("Error: unexpected reading of output parameter");
+			LOG_ERROR("unexpected reading of output parameter");
 			return ERROR_JTAG_DEVICE_ERROR;
 		}

@ -181,7 +181,7 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad
 		&& (address < MIPS64_PRACC_PARAM_IN + ctx->num_iparam * MIPS64_PRACC_DATA_STEP)) {
 		offset = (address - MIPS64_PRACC_PARAM_IN) / MIPS64_PRACC_DATA_STEP;
 		if (!ctx->local_iparam) {
-			LOG_ERROR("Error: unexpected writing of input parameter");
+			LOG_ERROR("unexpected writing of input parameter");
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 		ctx->local_iparam[offset] = data;
@ -189,14 +189,14 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad
 		&& (address < MIPS64_PRACC_PARAM_OUT + ctx->num_oparam * MIPS64_PRACC_DATA_STEP)) {
 		offset = (address - MIPS64_PRACC_PARAM_OUT) / MIPS64_PRACC_DATA_STEP;
 		if (!ctx->local_oparam) {
-			LOG_ERROR("Error: unexpected writing of output parameter");
+			LOG_ERROR("unexpected writing of output parameter");
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 		ctx->local_oparam[offset] = data;
 	} else if (address == MIPS64_PRACC_STACK) {
 		/* save data onto our stack */
 		if (ctx->stack_offset >= STACK_DEPTH) {
-			LOG_ERROR("Error: PrAcc stack depth exceeded");
+			LOG_ERROR("PrAcc stack depth exceeded");
 			return ERROR_FAIL;
 		}
 		ctx->stack[ctx->stack_offset++] = data;
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@ -27,8 +27,8 @@
 #include "or1k.h"
 #include "or1k_du.h"

-LIST_HEAD(tap_list);
-LIST_HEAD(du_list);
+OOCD_LIST_HEAD(tap_list);
+OOCD_LIST_HEAD(du_list);

 static int or1k_remove_breakpoint(struct target *target,
 				  struct breakpoint *breakpoint);
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@ -206,7 +206,7 @@ typedef struct {
 	bool haltgroup_supported;
 } riscv013_info_t;

-static LIST_HEAD(dm_list);
+static OOCD_LIST_HEAD(dm_list);

 static riscv013_info_t *get_info(const struct target *target)
 {
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@ -2911,7 +2911,7 @@ static int riscv_resume(

 	struct list_head *targets;

-	LIST_HEAD(single_target_list);
+	OOCD_LIST_HEAD(single_target_list);
 	struct target_list single_target_entry = {
 		.lh = {NULL, NULL},
 		.target = target
@ -4030,7 +4030,7 @@ int riscv_openocd_poll(struct target *target)

 	struct list_head *targets;

-	LIST_HEAD(single_target_list);
+	OOCD_LIST_HEAD(single_target_list);
 	struct target_list single_target_entry = {
 		.lh = {NULL, NULL},
 		.target = target
--- a/src/target/target.c
+++ b/src/target/target.c
@ -108,10 +108,10 @@ struct target *all_targets;
 static struct target_event_callback *target_event_callbacks;
 static struct target_timer_callback *target_timer_callbacks;
 static int64_t target_timer_next_event_value;
-static LIST_HEAD(target_reset_callback_list);
-static LIST_HEAD(target_trace_callback_list);
+static OOCD_LIST_HEAD(target_reset_callback_list);
+static OOCD_LIST_HEAD(target_trace_callback_list);
 static const unsigned int polling_interval = TARGET_DEFAULT_POLLING_INTERVAL;
-static LIST_HEAD(empty_smp_targets);
+static OOCD_LIST_HEAD(empty_smp_targets);

 enum nvp_assert {
 	NVP_DEASSERT,
@ -5832,6 +5832,7 @@ static int target_create(struct jim_getopt_info *goi)
 		free(target->gdb_port_override);
 		free(target->trace_info);
 		free(target->type);
+		free(target->private_config);
 		free(target);
 		return e;
 	}
@ -5849,6 +5850,7 @@ static int target_create(struct jim_getopt_info *goi)
 		free(target->gdb_port_override);
 		free(target->trace_info);
 		free(target->type);
+		free(target->private_config);
 		free(target);
 		return JIM_ERR;
 	}
@ -5862,6 +5864,7 @@ static int target_create(struct jim_getopt_info *goi)
 			free(target->gdb_port_override);
 			free(target->trace_info);
 			free(target->type);
+			free(target->private_config);
 			free(target);
 			return JIM_ERR;
 		}
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@ -503,7 +503,7 @@ static enum xtensa_reg_id xtensa_windowbase_offset_to_canonical(struct xtensa *x
 	} else if (reg_idx >= XT_REG_IDX_A0 && reg_idx <= XT_REG_IDX_A15) {
 		idx = reg_idx - XT_REG_IDX_A0;
 	} else {
-		LOG_ERROR("Error: can't convert register %d to non-windowbased register!", reg_idx);
+		LOG_ERROR("Can't convert register %d to non-windowbased register", reg_idx);
 		return -1;
 	}
 	/* Each windowbase value represents 4 registers on LX and 8 on NX */
--- a/tcl/board/nordic/nrf54l15-dk.cfg
+++ b/tcl/board/nordic/nrf54l15-dk.cfg
@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic Semiconductor nRF54L15 Development kit
+# https://www.nordicsemi.com/Products/Development-hardware/nRF54L15-DK
+#
+
+source [find interface/jlink.cfg]
+source [find target/nordic/nrf54l.cfg]
--- a/tcl/board/st_nucleo_c0.cfg
+++ b/tcl/board/st_nucleo_c0.cfg
@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find interface/stlink.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32c0x.cfg]
+
+reset_config srst_only
--- a/tcl/interface/raspberrypi5-gpiod.cfg
+++ b/tcl/interface/raspberrypi5-gpiod.cfg
@ -18,11 +18,19 @@ proc read_file { name } {
 	return $result
 }

+proc find_rp1_alias {} {
+	foreach f [glob -directory "/proc/device-tree/aliases" "gpio\[0-9\]"] {
+		if {[string match "*/rp1/*" [read_file $f]]} {
+			return $f
+		}
+	}
+}
+
 set pcie_aspm [read_file /sys/module/pcie_aspm/parameters/policy]
 if {![string match {*\[performance\]*} $pcie_aspm]} {
 	echo "Warn : Switch PCIe power saving off or the first couple of pulses gets clocked as fast as 20 MHz"
 	echo "Warn : Issue 'echo performance | sudo tee /sys/module/pcie_aspm/parameters/policy'"
 }

-set GPIO_CHIP 4
+set GPIO_CHIP [string index [find_rp1_alias] end]
 source [find interface/raspberrypi-gpio-connector.cfg]
--- a/tcl/target/nordic/nrf54l.cfg
+++ b/tcl/target/nordic/nrf54l.cfg
@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF54L series
+#
+# Arm Cortex-M33 processor with RISC-V coprocessor
+#
+# The device uses resistive RAM (RRAM) as non-volatile memory.
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME nrf54l
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 16 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba02477
+}
+
+transport select swd
+
+swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# Create target for the control access port (CTRL-AP).
+target create $_CHIPNAME.ctrl mem_ap -dap $_CHIPNAME.dap -ap-num 1
+
+adapter speed 1000
+
+# Use main processor as default target.
+targets $_TARGETNAME
+
+if {![using_hla]} {
+	$_TARGETNAME cortex_m reset_config sysresetreq
+}
--- a/tcl/target/stm32u0x.cfg
+++ b/tcl/target/stm32u0x.cfg
@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for STM32U0x series.
+#
+# STM32U0 devices support only SWD transport.
+#
+
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32u0x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x6ba02477
+}
+
+swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1FFF6800 0 0 0 $_TARGETNAME
+
+adapter speed 2000
+
+if {![using_hla]} {
+	# Use SYSRESETREQ to perform a soft reset if SRST is not fitted.
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power).
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters when core is halted.
+	# DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}