Selecting dbus is sometimes necessary.
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25e8b66b08
commit
041e0ccf9e
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@ -12,6 +12,13 @@
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#include "opcodes.h"
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#include "opcodes.h"
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#include "register.h"
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#include "register.h"
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/**
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* Since almost everything can be accomplish by scanning the dbus register, all
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* functions here assume dbus is already selected. The exception are functions
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* called directly by OpenOCD, which can't assume anything about what's
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* currently in IR. They should set IR to dbus explicitly.
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*/
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#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
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#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
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#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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@ -238,9 +245,6 @@ static uint32_t dtminfo_read(struct target *target)
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}
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}
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/* Always return to dbus. */
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/* Always return to dbus. */
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/* TODO: Can we rely on IR not being messed with between calls into
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* RISCV code? Eg. what happens if there are multiple cores and some
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* other core is accessed? */
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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return buf_get_u32(field.in_value, 0, 32);
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return buf_get_u32(field.in_value, 0, 32);
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@ -457,6 +461,8 @@ static int riscv_examine(struct target *target)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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// Don't need to select dbus, since the first thing we do is read dtminfo.
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uint32_t dtminfo = dtminfo_read(target);
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uint32_t dtminfo = dtminfo_read(target);
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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@ -523,6 +529,7 @@ static int riscv_examine(struct target *target)
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static int riscv_poll(struct target *target)
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static int riscv_poll(struct target *target)
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{
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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bits_t bits = read_bits(target);
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bits_t bits = read_bits(target);
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if (bits.haltnot && bits.interrupt) {
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if (bits.haltnot && bits.interrupt) {
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@ -541,6 +548,7 @@ static int riscv_poll(struct target *target)
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static int riscv_halt(struct target *target)
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static int riscv_halt(struct target *target)
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{
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{
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LOG_DEBUG("riscv_halt()");
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LOG_DEBUG("riscv_halt()");
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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dram_write32(target, 0, csrsi(CSR_DCSR, DCSR_HALT), false);
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dram_write32(target, 0, csrsi(CSR_DCSR, DCSR_HALT), false);
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dram_write_jump(target, 1, true);
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dram_write_jump(target, 1, true);
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@ -550,6 +558,7 @@ static int riscv_halt(struct target *target)
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static int riscv_resume(struct target *target, int current, uint32_t address,
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static int riscv_resume(struct target *target, int current, uint32_t address,
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int handle_breakpoints, int debug_execution)
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int handle_breakpoints, int debug_execution)
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{
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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return resume(target, current, address, handle_breakpoints,
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return resume(target, current, address, handle_breakpoints,
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debug_execution, false);
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debug_execution, false);
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}
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}
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@ -557,6 +566,7 @@ static int riscv_resume(struct target *target, int current, uint32_t address,
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static int riscv_step(struct target *target, int current, uint32_t address,
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static int riscv_step(struct target *target, int current, uint32_t address,
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int handle_breakpoints)
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int handle_breakpoints)
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{
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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return resume(target, current, address, handle_breakpoints, 0, true);
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return resume(target, current, address, handle_breakpoints, 0, true);
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}
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}
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@ -564,6 +574,8 @@ static int riscv_assert_reset(struct target *target)
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{
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{
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// TODO: Maybe what I implemented here is more like soft_reset_halt()?
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// TODO: Maybe what I implemented here is more like soft_reset_halt()?
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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// The only assumption we can make is that the TAP was reset.
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// The only assumption we can make is that the TAP was reset.
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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LOG_ERROR("Debug interrupt didn't clear.");
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@ -592,6 +604,7 @@ static int riscv_assert_reset(struct target *target)
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static int riscv_deassert_reset(struct target *target)
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static int riscv_deassert_reset(struct target *target)
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{
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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if (target->reset_halt) {
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if (target->reset_halt) {
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return wait_for_state(target, TARGET_HALTED);
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return wait_for_state(target, TARGET_HALTED);
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} else {
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} else {
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@ -602,6 +615,7 @@ static int riscv_deassert_reset(struct target *target)
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static int riscv_read_memory(struct target *target, uint32_t address,
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static int riscv_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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// Plain implementation, where we write the address each time.
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// Plain implementation, where we write the address each time.
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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switch (size) {
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switch (size) {
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@ -667,6 +681,7 @@ static int riscv_read_memory(struct target *target, uint32_t address,
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static int riscv_write_memory(struct target *target, uint32_t address,
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static int riscv_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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// TODO: save/restore T0
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// TODO: save/restore T0
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// Set up the address.
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// Set up the address.
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