dsp563xx: minor fixes, code cleanup
This patch move the dsp563xx_target_create function to the related code block. Also the target examine function was added and the register cache is initialized in a separate function. The missing functionality to invalidate the x memory context on memory writes was also added.
This commit is contained in:
Mathias K
Øyvind Harboe
parent
b7163f534a
commit
01edbc2c3f
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@ -328,21 +328,6 @@ static int dsp563xx_write_core_reg(struct target *target, int num)
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return ERROR_OK;
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}
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static int dsp563xx_target_create(struct target *target, Jim_Interp * interp)
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{
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struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
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if (!dsp563xx)
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return ERROR_INVALID_ARGUMENTS;
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dsp563xx->jtag_info.tap = target->tap;
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target->arch_info = dsp563xx;
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dsp563xx->read_core_reg = dsp563xx_read_core_reg;
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dsp563xx->write_core_reg = dsp563xx_write_core_reg;
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return ERROR_OK;
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}
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static int dsp563xx_get_core_reg(struct reg *reg)
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{
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struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
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@ -379,6 +364,48 @@ static int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf)
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return ERROR_OK;
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}
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static const struct reg_arch_type dsp563xx_reg_type = {
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.get = dsp563xx_get_core_reg,
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.set = dsp563xx_set_core_reg,
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};
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static void dsp563xx_build_reg_cache(struct target *target)
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{
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struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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struct reg_cache *cache = malloc(sizeof(struct reg_cache));
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struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS);
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struct dsp563xx_core_reg *arch_info = malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
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int i;
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/* Build the process context cache */
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cache->name = "dsp563xx registers";
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cache->next = NULL;
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cache->reg_list = reg_list;
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cache->num_regs = DSP563XX_NUMCOREREGS;
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(*cache_p) = cache;
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dsp563xx->core_cache = cache;
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for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
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{
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arch_info[i].num = dsp563xx_regs[i].id;
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arch_info[i].name = dsp563xx_regs[i].name;
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arch_info[i].size = dsp563xx_regs[i].bits;
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arch_info[i].eame = dsp563xx_regs[i].eame;
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arch_info[i].instr_mask = dsp563xx_regs[i].instr_mask;
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arch_info[i].target = target;
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arch_info[i].dsp563xx_common = dsp563xx;
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reg_list[i].name = dsp563xx_regs[i].name;
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reg_list[i].size = dsp563xx_regs[i].bits;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].type = &dsp563xx_reg_type;
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reg_list[i].arch_info = &arch_info[i];
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}
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}
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static int dsp563xx_read_register(struct target *target, int num, int force);
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static int dsp563xx_write_register(struct target *target, int num, int force);
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@ -747,48 +774,76 @@ static int dsp563xx_restore_context(struct target *target)
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return err;
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}
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static const struct reg_arch_type dsp563xx_reg_type = {
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.get = dsp563xx_get_core_reg,
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.set = dsp563xx_set_core_reg,
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};
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static void dsp563xx_invalidate_x_context(struct target *target, uint32_t addr_start, uint32_t addr_end )
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{
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int i;
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struct dsp563xx_core_reg *arch_info;
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struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
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if ( addr_start > ASM_REG_W_IPRC )
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return;
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if ( addr_start < ASM_REG_W_AAR3 )
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return;
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for (i = REG_NUM_IPRC; i < DSP563XX_NUMCOREREGS; i++)
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{
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arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
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if ( (arch_info->instr_mask >= addr_start) &&
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(arch_info->instr_mask <= addr_end))
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{
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dsp563xx->core_cache->reg_list[i].valid = 0;
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dsp563xx->core_cache->reg_list[i].dirty = 0;
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}
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}
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}
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static int dsp563xx_target_create(struct target *target, Jim_Interp * interp)
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{
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struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
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if (!dsp563xx)
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return ERROR_INVALID_ARGUMENTS;
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dsp563xx->jtag_info.tap = target->tap;
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target->arch_info = dsp563xx;
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dsp563xx->read_core_reg = dsp563xx_read_core_reg;
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dsp563xx->write_core_reg = dsp563xx_write_core_reg;
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return ERROR_OK;
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}
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static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
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{
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/* get pointers to arch-specific information */
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struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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struct reg_cache *cache = malloc(sizeof(struct reg_cache));
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struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS);
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struct dsp563xx_core_reg *arch_info = malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
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int i;
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LOG_DEBUG("%s", __FUNCTION__);
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/* Build the process context cache */
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cache->name = "dsp563xx registers";
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cache->next = NULL;
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cache->reg_list = reg_list;
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cache->num_regs = DSP563XX_NUMCOREREGS;
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(*cache_p) = cache;
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dsp563xx->core_cache = cache;
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dsp563xx_build_reg_cache(target);
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for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
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return ERROR_OK;
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}
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static int dsp563xx_examine(struct target *target)
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{
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arch_info[i].num = dsp563xx_regs[i].id;
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arch_info[i].name = dsp563xx_regs[i].name;
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arch_info[i].size = dsp563xx_regs[i].bits;
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arch_info[i].eame = dsp563xx_regs[i].eame;
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arch_info[i].instr_mask = dsp563xx_regs[i].instr_mask;
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arch_info[i].target = target;
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arch_info[i].dsp563xx_common = dsp563xx;
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reg_list[i].name = dsp563xx_regs[i].name;
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reg_list[i].size = dsp563xx_regs[i].bits;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].type = &dsp563xx_reg_type;
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reg_list[i].arch_info = &arch_info[i];
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uint32_t chip;
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if (target->tap->hasidcode == false)
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{
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LOG_ERROR("no IDCODE present on device");
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return ERROR_INVALID_ARGUMENTS;
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}
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if (!target_was_examined(target))
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{
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target_set_examined(target);
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/* examine core and chip derivate number */
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chip = (target->tap->idcode>>12)&0x3ff;
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/* core number 0 means DSP563XX */
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if ( ((chip>>5)&0x1f) == 0 )
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chip += 300;
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LOG_INFO("DSP56%03d device found",chip);
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}
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return ERROR_OK;
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@ -913,7 +968,7 @@ static int dsp563xx_poll(struct target *target)
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if ((err = dsp563xx_debug_init(target)) != ERROR_OK)
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return err;
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LOG_DEBUG("target->state: %s", target_state_name(target));
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LOG_DEBUG("target->state: %s (%x)", target_state_name(target),once_status);
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}
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}
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@ -1158,7 +1213,7 @@ static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t ad
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}
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/* we only support 4 byte aligned data */
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if ( size != 4 )
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if ( (size != 4) || (!count) )
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{
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return ERROR_INVALID_ARGUMENTS;
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}
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@ -1250,7 +1305,7 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a
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}
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/* we only support 4 byte aligned data */
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if ( size != 4 )
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if ( (size != 4) || (!count) )
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{
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return ERROR_INVALID_ARGUMENTS;
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}
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@ -1258,6 +1313,8 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a
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switch (mem_type)
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{
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case MEM_X:
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/* invalidate affected x registers */
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dsp563xx_invalidate_x_context(target,address,address+count-1);
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move_cmd = 0x615800;
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break;
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case MEM_Y:
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@ -1546,4 +1603,5 @@ struct target_type dsp563xx_target = {
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.commands = dsp563xx_command_handlers,
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.target_create = dsp563xx_target_create,
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.init_target = dsp563xx_init_target,
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.examine = dsp563xx_examine,
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};
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