David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle more 32-bit instructions: A5.3.1 Data processing (modified immediate) My small sample shows GCC likes to use many of these instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch
parent
8b89224c6e
commit
0165ae4405
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@ -2532,6 +2532,144 @@ undef:
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return ERROR_INVALID_ARGUMENTS;
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return ERROR_INVALID_ARGUMENTS;
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}
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}
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static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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char *mnemonic = NULL;
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int rn = (opcode >> 16) & 0xf;
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int rd = (opcode >> 8) & 0xf;
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unsigned immed = opcode & 0xff;
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unsigned func;
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bool one = false;
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char *suffix = "";
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/* ARMv7-M: A5.3.2 Modified immediate constants */
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func = (opcode >> 11) & 0x0e;
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if (immed & 0x80)
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func |= 1;
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if (opcode & (1 << 26))
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func |= 0x10;
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/* "Modified" immediates */
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switch (func >> 1) {
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case 0:
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break;
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case 2:
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immed <<= 8;
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/* FALLTHROUGH */
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case 1:
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immed += immed << 16;
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break;
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case 3:
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immed += immed << 8;
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immed += immed << 16;
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break;
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default:
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immed |= 0x80;
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immed = ror(immed, func);
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}
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if (opcode & (1 << 20))
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suffix = "S";
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switch ((opcode >> 21) & 0xf) {
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case 0:
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if (rd == 0xf) {
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instruction->type = ARM_TST;
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mnemonic = "TST";
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one = true;
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suffix = "";
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rd = rn;
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} else {
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instruction->type = ARM_AND;
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mnemonic = "AND";
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}
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break;
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case 1:
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instruction->type = ARM_BIC;
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mnemonic = "BIC";
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break;
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case 2:
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if (rn == 0xf) {
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instruction->type = ARM_MOV;
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mnemonic = "MOV";
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one = true;
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} else {
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instruction->type = ARM_ORR;
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mnemonic = "ORR";
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}
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break;
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case 3:
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if (rn == 0xf) {
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instruction->type = ARM_MVN;
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mnemonic = "MVN";
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one = true;
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} else {
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// instruction->type = ARM_ORN;
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mnemonic = "ORN";
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}
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break;
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case 4:
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if (rd == 0xf) {
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instruction->type = ARM_TEQ;
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mnemonic = "TEQ";
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one = true;
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suffix = "";
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rd = rn;
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} else {
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instruction->type = ARM_EOR;
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mnemonic = "EOR";
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}
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break;
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case 8:
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if (rd == 0xf) {
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instruction->type = ARM_CMN;
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mnemonic = "CMN";
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one = true;
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suffix = "";
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rd = rn;
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} else {
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instruction->type = ARM_ADD;
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mnemonic = "ADD";
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}
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break;
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case 10:
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instruction->type = ARM_ADC;
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mnemonic = "ADC";
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break;
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case 11:
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instruction->type = ARM_SBC;
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mnemonic = "SBC";
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break;
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case 13:
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if (rd == 0xf) {
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instruction->type = ARM_CMP;
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mnemonic = "CMP";
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one = true;
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suffix = "";
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rd = rn;
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} else {
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instruction->type = ARM_SUB;
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mnemonic = "SUB";
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}
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break;
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case 14:
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instruction->type = ARM_RSB;
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mnemonic = "RSB";
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break;
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default:
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return ERROR_INVALID_ARGUMENTS;
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}
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if (one)
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sprintf(cp, "%s\tr%d, #%d\t; %#8.8x",
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mnemonic, rd, immed, immed);
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else
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sprintf(cp, "%s%s\tr%d, r%d, #%d\t; %#8.8x",
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mnemonic, suffix, rd, rn, immed, immed);
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return ERROR_OK;
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}
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/*
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/*
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* REVISIT for Thumb2 instructions, instruction->type and friends aren't
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* REVISIT for Thumb2 instructions, instruction->type and friends aren't
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@ -2580,8 +2718,12 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
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cp = strchr(instruction->text, 0);
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cp = strchr(instruction->text, 0);
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retval = ERROR_FAIL;
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retval = ERROR_FAIL;
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/* ARMv7-M: A5.3.1 Data processing (modified immediate) */
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if ((opcode & 0x1a008000) == 0x10000000)
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retval = t2ev_data_mod_immed(opcode, address, instruction, cp);
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/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
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/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
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if ((opcode & 0x18008000) == 0x10008000)
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else if ((opcode & 0x18008000) == 0x10008000)
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retval = t2ev_b_misc(opcode, address, instruction, cp);
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retval = t2ev_b_misc(opcode, address, instruction, cp);
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/* FIXME decode more 32-bit instructions */
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/* FIXME decode more 32-bit instructions */
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