target/mips32: add dsp access support for gdb
Change order of dsp register name array and removed hi0 and lo0 to comply with gdb definition of dsp in mips-dsp.xml, the regs name array is now mapping corresponding dsp accumulator names onto `mips32_regs` and `core_regs` instead of mapping to instr arrays in dsp functions. feature now requires a place to store cached dsp registers. Add dsp registers to reg_list for gdb to access them. Add dsp module enable detection to avoid DSP Disabled exception while reading dsp accumulators. Add dsp register reading procedure in `mips32_pracc_read_regs` and writing procedure in `mips32_pracc_write_regs`. Change-Id: Iacc335da030ab85989922c81aac7925b3dc17459 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8476 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Walter Ji
Antonio Borneo
parent
ab31562131
commit
00ee9b09d9
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@ -31,7 +31,7 @@ static const char *mips_isa_strings[] = {
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/*
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* GDB registers
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* based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu}.xml
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* based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu,dsp}.xml
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*/
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static const struct {
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unsigned id;
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@ -156,6 +156,22 @@ static const struct {
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"org.gnu.gdb.mips.cpu", 0 },
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{ MIPS32_REGLIST_C0_GUESTCTL1_INDEX, "guestCtl1", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.cp0", 0 },
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{ MIPS32_REGLIST_DSP_INDEX + 0, "hi1", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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{ MIPS32_REGLIST_DSP_INDEX + 1, "lo1", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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{ MIPS32_REGLIST_DSP_INDEX + 2, "hi2", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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{ MIPS32_REGLIST_DSP_INDEX + 3, "lo2", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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{ MIPS32_REGLIST_DSP_INDEX + 4, "hi3", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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{ MIPS32_REGLIST_DSP_INDEX + 5, "lo3", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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{ MIPS32_REGLIST_DSP_DSPCTL_INDEX, "dspctl", REG_TYPE_INT, NULL,
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"org.gnu.gdb.mips.dsp", 0 },
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};
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#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
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@ -211,13 +227,11 @@ static const struct {
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static const struct {
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const char *name;
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} mips32_dsp_regs[MIPS32NUMDSPREGS] = {
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{ "hi0"},
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{ "hi1"},
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{ "hi2"},
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{ "hi3"},
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{ "lo0"},
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{ "lo1"},
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{ "hi2"},
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{ "lo2"},
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{ "hi3"},
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{ "lo3"},
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{ "control"},
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};
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@ -328,7 +342,12 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
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if (num >= MIPS32_NUM_REGS)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (num >= MIPS32_REGLIST_C0_INDEX) {
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if (num >= MIPS32_REGLIST_DSP_INDEX) {
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/* DSP */
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cnum = num - MIPS32_REGLIST_DSP_INDEX;
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reg_value = mips32->core_regs.dsp[cnum];
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buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
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} else if (num >= MIPS32_REGLIST_C0_INDEX) {
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/* CP0 */
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cnum = num - MIPS32_REGLIST_C0_INDEX;
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reg_value = mips32->core_regs.cp0[cnum];
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@ -371,7 +390,12 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
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if (num >= MIPS32_NUM_REGS)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (num >= MIPS32_REGLIST_C0_INDEX) {
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if (num >= MIPS32_REGLIST_DSP_INDEX) {
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/* DSP */
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cnum = num - MIPS32_REGLIST_DSP_INDEX;
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reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
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mips32->core_regs.dsp[cnum] = (uint32_t)reg_value;
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} else if (num >= MIPS32_REGLIST_C0_INDEX) {
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/* CP0 */
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cnum = num - MIPS32_REGLIST_C0_INDEX;
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reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
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@ -1026,10 +1050,20 @@ int mips32_cpu_probe(struct target *target)
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/* reads dsp implementation info from CP0 Config3 register {DSPP, DSPREV}*/
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static void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
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{
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uint32_t dsp_present = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPP_MASK) >> MIPS32_CONFIG3_DSPP_SHIFT);
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uint32_t retval, status_value, dsp_present;
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bool dsp_enabled;
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retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to read cp0 status register");
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return;
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}
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dsp_present = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPP_MASK) >> MIPS32_CONFIG3_DSPP_SHIFT);
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dsp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0;
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if (dsp_present) {
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mips32->dsp_imp = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPREV_MASK) >> MIPS32_CONFIG3_DSPREV_SHIFT) + 1;
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LOG_USER("DSP implemented: %s, rev %d", "yes", mips32->dsp_imp);
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LOG_USER("DSP implemented: rev %d, %s", mips32->dsp_imp, dsp_enabled ? "enabled" : "disabled");
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} else {
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LOG_USER("DSP implemented: %s", "no");
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}
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@ -1747,13 +1781,11 @@ static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *va
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};
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uint32_t dsp_read_code[] = {
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MIPS32_MFHI(isa, t0), /* mfhi t0 ($ac0) - OPCODE - 0x00004010 */
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MIPS32_DSP_MFHI(t0, 1), /* mfhi t0,$ac1 - OPCODE - 0x00204010 */
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MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */
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MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/
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MIPS32_MFLO(isa, t0), /* mflo t0 ($ac0) - OPCODE - 0x00004012 */
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MIPS32_DSP_MFLO(t0, 1), /* mflo t0,$ac1 - OPCODE - 0x00204012 */
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MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */
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MIPS32_DSP_MFLO(t0, 2), /* mflo t0,$ac2 - OPCODE - 0x00404012 */
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MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/
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MIPS32_DSP_MFLO(t0, 3), /* mflo t0,$ac3 - OPCODE - 0x00604012 */
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MIPS32_DSP_RDDSP(t0, 0x3F), /* rddsp t0, 0x3f (DSPCtl) - OPCODE - 0x7c3f44b8 */
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};
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@ -1824,13 +1856,11 @@ static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t va
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};
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uint32_t dsp_write_code[] = {
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MIPS32_MTHI(isa, t0), /* mthi t0 ($ac0) - OPCODE - 0x01000011 */
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MIPS32_DSP_MTHI(t0, 1), /* mthi t0, $ac1 - OPCODE - 0x01000811 */
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MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */
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MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */
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MIPS32_MTLO(isa, t0), /* mtlo t0 ($ac0) - OPCODE - 0x01000013 */
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MIPS32_DSP_MTLO(t0, 1), /* mtlo t0, $ac1 - OPCODE - 0x01000813 */
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MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */
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MIPS32_DSP_MTLO(t0, 2), /* mtlo t0, $ac2 - OPCODE - 0x01001013 */
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MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */
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MIPS32_DSP_MTLO(t0, 3), /* mtlo t0, $ac3 - OPCODE - 0x01001813 */
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MIPS32_DSP_WRDSP(t0, 0x1F), /* wrdsp t0, 0x1f (DSPCtl) - OPCODE - 0x7d00fcf8*/
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};
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@ -2107,15 +2137,18 @@ static int mips32_dsp_find_register_by_name(const char *reg_name)
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*
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* @return ERROR_OK on success; error code on failure.
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*/
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static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
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static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips32_common *mips32)
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{
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uint32_t value = 0;
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
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int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, i);
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if (retval != ERROR_OK) {
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command_print(CMD, "couldn't access reg %s", mips32_dsp_regs[i].name);
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return retval;
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}
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mips32->core_regs.dsp[i] = value;
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mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + i].dirty = 1;
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command_print(CMD, "%*s: 0x%8.8x", 7, mips32_dsp_regs[i].name, value);
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}
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return ERROR_OK;
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@ -2132,20 +2165,28 @@ static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips_e
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*
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* @return ERROR_OK on success; error code on failure.
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*/
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static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
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static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips32_common *mips32)
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{
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uint32_t value = 0;
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int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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if (index == MIPS32NUMDSPREGS) {
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command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, index);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK) {
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command_print(CMD, "ERROR: Could not access dsp register %s", CMD_ARGV[0]);
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else
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command_print(CMD, "0x%8.8x", value);
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return retval;
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}
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command_print(CMD, "0x%8.8x", value);
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if (mips32->core_regs.dsp[index] != value) {
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mips32->core_regs.dsp[index] = value;
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mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1;
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}
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return retval;
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}
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@ -2162,9 +2203,10 @@ static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips_e
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*
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* @return ERROR_OK on success; error code on failure.
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*/
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static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
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static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips32_common *mips32)
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{
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uint32_t value;
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
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if (index == MIPS32NUMDSPREGS) {
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command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
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@ -2174,8 +2216,13 @@ static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips_e
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
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int retval = mips32_pracc_write_dsp_reg(ejtag_info, value, index);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK) {
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command_print(CMD, "Error: could not write to dsp register %s", CMD_ARGV[0]);
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return retval;
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}
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mips32->core_regs.dsp[index] = value;
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mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1;
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return retval;
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}
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@ -2193,7 +2240,6 @@ COMMAND_HANDLER(mips32_handle_dsp_command)
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int retval, tmp;
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struct target *target = get_current_target(CMD_CTX);
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struct mips32_common *mips32 = target_to_mips32(target);
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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retval = mips32_verify_pointer(CMD, mips32);
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if (retval != ERROR_OK)
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@ -2217,10 +2263,10 @@ COMMAND_HANDLER(mips32_handle_dsp_command)
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switch (CMD_ARGC) {
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case 0:
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retval = mips32_dsp_get_all_regs(CMD, ejtag_info);
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retval = mips32_dsp_get_all_regs(CMD, mips32);
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break;
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case 1:
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retval = mips32_dsp_get_register(CMD, ejtag_info);
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retval = mips32_dsp_get_register(CMD, mips32);
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break;
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case 2:
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tmp = *CMD_ARGV[0];
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@ -2228,7 +2274,7 @@ COMMAND_HANDLER(mips32_handle_dsp_command)
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command_print(CMD, "Error: invalid dsp command format");
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retval = ERROR_COMMAND_ARGUMENT_INVALID;
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} else {
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retval = mips32_dsp_set_register(CMD, ejtag_info);
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retval = mips32_dsp_set_register(CMD, mips32);
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}
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break;
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default:
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@ -69,7 +69,7 @@
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#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
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#define MIPS32NUMDSPREGS 9
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#define MIPS32NUMDSPREGS 7
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/* Bit Mask indicating CP0 register supported by this core */
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#define MIPS_CP0_MK4 0x0001
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@ -78,6 +78,7 @@
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#define MIPS_CP0_IAPTIV 0x0008
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/* CP0 Status register fields */
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#define MIPS32_CP0_STATUS_MX_SHIFT 24
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#define MIPS32_CP0_STATUS_FR_SHIFT 26
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#define MIPS32_CP0_STATUS_CU1_SHIFT 29
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@ -211,6 +212,7 @@ static const struct mips32_cp0 {
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enum {
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MIPS32_PC = 37,
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MIPS32_FIR = 71,
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MIPS32_DSPCTL = 78,
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MIPS32NUMCOREREGS
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};
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@ -220,11 +222,13 @@ enum {
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#define MIPS32_REG_FP_COUNT 32
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#define MIPS32_REG_FPC_COUNT 2
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#define MIPS32_REG_C0_COUNT 5
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#define MIPS32_REG_DSP_COUNT 7
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#define MIPS32_REGLIST_GP_INDEX 0
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#define MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)
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#define MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)
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#define MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)
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#define MIPS32_REGLIST_DSP_INDEX (MIPS32_REGLIST_C0_INDEX + MIPS32_REG_C0_COUNT)
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#define MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0)
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#define MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1)
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@ -238,6 +242,10 @@ enum {
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#define MIPS32_REG_C0_PC_INDEX 3
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#define MIPS32_REG_C0_GUESTCTL1_INDEX 4
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#define MIPS32_REGLIST_DSP_DSPCTL_INDEX (MIPS32_REGLIST_DSP_INDEX + 6)
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#define MIPS32_REG_DSP_DSPCTL_INDEX 6
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enum mips32_isa_mode {
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MIPS32_ISA_MIPS32 = 0,
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MIPS32_ISA_MIPS16E = 1,
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@ -377,6 +385,7 @@ struct mips32_core_regs {
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uint64_t fpr[MIPS32_REG_FP_COUNT];
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uint32_t fpcr[MIPS32_REG_FPC_COUNT];
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uint32_t cp0[MIPS32_REG_C0_COUNT];
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uint32_t dsp[MIPS32_REG_DSP_COUNT];
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};
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struct mips32_common {
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@ -878,6 +878,7 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
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uint32_t *c0rs = mips32->core_regs.cp0;
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bool fpu_in_64bit = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
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bool fp_enabled = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
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bool dsp_enabled = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0);
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uint32_t rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
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pracc_queue_init(&ctx);
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@ -943,6 +944,34 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
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pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
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}
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/* Store DSP Accumulators */
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if (mips32->dsp_imp && dsp_enabled) {
|
||||
/* Struct of mips32_dsp_regs: {ac{hi, lo}1-3, dspctl} */
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||||
uint32_t *dspr = mips32->core_regs.dsp;
|
||||
size_t dsp_regs = ARRAY_SIZE(mips32->core_regs.dsp);
|
||||
|
||||
/* Starts from ac1, core_regs.dsp contains dspctl register, therefore - 1 */
|
||||
for (size_t index = 0; index != ((dsp_regs - 1) / 2); index++) {
|
||||
/* Every accumulator have 2 registers, hi and lo, and core_regs.dsp stores ac[1~3] */
|
||||
/* reads hi[ac] from core_regs array */
|
||||
pracc_add_li32(&ctx, 2, dspr[index * 2], 0);
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||||
/* reads lo[ac] from core_regs array */
|
||||
pracc_add_li32(&ctx, 3, dspr[(index * 2) + 1], 0);
|
||||
|
||||
/* Write to accumulator 1~3 and index starts from 0, therefore ac = index + 1 */
|
||||
size_t ac = index + 1;
|
||||
pracc_add(&ctx, 0, MIPS32_DSP_MTHI(2, ac));
|
||||
pracc_add(&ctx, 0, MIPS32_DSP_MTLO(3, ac));
|
||||
}
|
||||
|
||||
/* DSPCTL is the last element of register store */
|
||||
pracc_add_li32(&ctx, 2, dspr[6], 0);
|
||||
pracc_add(&ctx, 0, MIPS32_DSP_WRDSP(2, 0x1F));
|
||||
|
||||
if (rel > MIPS32_RELEASE_1)
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
}
|
||||
|
||||
/* load registers 2 to 31 with li32, optimize */
|
||||
for (int i = 2; i < 32; i++)
|
||||
pracc_add_li32(&ctx, i, gprs[i], 1);
|
||||
|
|
@ -1064,14 +1093,16 @@ int mips32_pracc_read_regs(struct mips32_common *mips32)
|
|||
unsigned int offset_cp0 = ((uint8_t *)&core_regs->cp0[0]) - (uint8_t *)core_regs;
|
||||
unsigned int offset_fpr = ((uint8_t *)&core_regs->fpr[0]) - (uint8_t *)core_regs;
|
||||
unsigned int offset_fpcr = ((uint8_t *)&core_regs->fpcr[0]) - (uint8_t *)core_regs;
|
||||
bool fp_enabled;
|
||||
unsigned int offset_dsp = ((uint8_t *)&core_regs->dsp[0]) - (uint8_t *)core_regs;
|
||||
bool fp_enabled, dsp_enabled;
|
||||
|
||||
/*
|
||||
* This procedure has to be in 2 distinctive steps, because we can
|
||||
* only know whether FP is enabled after reading CP0.
|
||||
* This procedure has to be in 3 distinctive steps, because we can
|
||||
* only know whether FP and DSP are enabled after reading CP0.
|
||||
*
|
||||
* Step 1: Read everything except CP1 stuff
|
||||
* Step 1: Read everything except CP1 and DSP stuff
|
||||
* Step 2: Read CP1 stuff if FP is implemented
|
||||
* Step 3: Read DSP registers if dsp is implemented
|
||||
*/
|
||||
|
||||
pracc_queue_init(&ctx);
|
||||
|
|
@ -1149,6 +1180,50 @@ int mips32_pracc_read_regs(struct mips32_common *mips32)
|
|||
|
||||
pracc_queue_free(&ctx);
|
||||
}
|
||||
|
||||
dsp_enabled = (mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0;
|
||||
if (mips32->dsp_imp && dsp_enabled) {
|
||||
pracc_queue_init(&ctx);
|
||||
|
||||
mips32_pracc_store_regs_set_base_addr(&ctx);
|
||||
|
||||
/* Struct of mips32_dsp_regs[7]: {ac{hi, lo}1-3, dspctl} */
|
||||
size_t dsp_regs = ARRAY_SIZE(mips32->core_regs.dsp);
|
||||
/* Starts from ac1, core_regs.dsp have dspctl register, therefore - 1 */
|
||||
for (size_t index = 0; index != ((dsp_regs - 1) / 2); index++) {
|
||||
/* Every accumulator have 2 registers, hi&lo, and core_regs.dsp stores ac[1~3] */
|
||||
/* Reads offset of hi[ac] from core_regs array */
|
||||
size_t offset_hi = offset_dsp + ((index * 2) * sizeof(uint32_t));
|
||||
/* Reads offset of lo[ac] from core_regs array */
|
||||
size_t offset_lo = offset_dsp + (((index * 2) + 1) * sizeof(uint32_t));
|
||||
|
||||
/* DSP Ac registers starts from 1 and index starts from 0, therefore ac = index + 1 */
|
||||
size_t ac = index + 1;
|
||||
pracc_add(&ctx, 0, MIPS32_DSP_MFHI(8, ac));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_hi,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_hi, 1));
|
||||
pracc_add(&ctx, 0, MIPS32_DSP_MFLO(8, ac));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_lo,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_lo, 1));
|
||||
}
|
||||
|
||||
/* DSPCTL is the last element of register store */
|
||||
pracc_add(&ctx, 0, MIPS32_DSP_RDDSP(8, 0x3F));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_dsp + ((dsp_regs - 1) * sizeof(uint32_t)),
|
||||
MIPS32_SW(ctx.isa, 8,
|
||||
PRACC_OUT_OFFSET + offset_dsp + ((dsp_regs - 1) * sizeof(uint32_t)), 1));
|
||||
|
||||
mips32_pracc_store_regs_restore(&ctx);
|
||||
|
||||
/* jump to start */
|
||||
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
|
||||
/* load $15 in DeSave */
|
||||
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
|
||||
|
||||
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1);
|
||||
|
||||
pracc_queue_free(&ctx);
|
||||
}
|
||||
return ctx.retval;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue