interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cortex_a/r/m: fix handling of un-examined cores 

On multi-core systems, with some cores in power-down state, examination
will fail for these cores. Make sure assert- and deassert_reset functions
don't crash due to uninitialized variables.

Change-Id: I472f8d19af2cd3c770c05f3e57a31b35a863b687
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3552
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Matthias Welwarsky 2016-08-05 21:50:33 +02:00 committed by Freddie Chopin
parent 75c3f4a25c
commit 0099430104
2 changed files with 31 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/target/cortex_a.c
View File

@ -853,7 +853,8 @@ static int cortex_a_halt_smp(struct target *target)
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
if ((curr != target) && (curr->state != TARGET_HALTED))
if ((curr != target) && (curr->state != TARGET_HALTED)
&& target_was_examined(curr))
retval += cortex_a_halt(curr);
head = head->next;
}
@ -1156,7 +1157,8 @@ static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
if ((curr != target) && (curr->state != TARGET_RUNNING)) {
if ((curr != target) && (curr->state != TARGET_RUNNING)
&& target_was_examined(curr)) {
/* resume current address , not in step mode */
retval += cortex_a_internal_restore(curr, 1, &address,
handle_breakpoints, 0);
@ -1936,6 +1938,7 @@ static int cortex_a_assert_reset(struct target *target)
}
/* registers are now invalid */
if (target_was_examined(target))
register_cache_invalidate(armv7a->arm.core_cache);
target->state = TARGET_RESET;
@ -1952,17 +1955,22 @@ static int cortex_a_deassert_reset(struct target *target)
/* be certain SRST is off */
jtag_add_reset(0, 0);
if (target_was_examined(target)) {
retval = cortex_a_poll(target);
if (retval != ERROR_OK)
return retval;
}
if (target->reset_halt) {
if (target->state != TARGET_HALTED) {
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
if (target_was_examined(target)) {
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
} else
target->state = TARGET_UNKNOWN;
}
}

15
src/target/cortex_m.c
View File

@ -981,6 +981,18 @@ static int cortex_m_assert_reset(struct target *target)
bool srst_asserted = false;
if (!target_was_examined(target)) {
if (jtag_reset_config & RESET_HAS_SRST) {
adapter_assert_reset();
if (target->reset_halt)
LOG_ERROR("Target not examined, will not halt after reset!");
return ERROR_OK;
} else {
LOG_ERROR("Target not examined, reset NOT asserted!");
return ERROR_FAIL;
}
}
if ((jtag_reset_config & RESET_HAS_SRST) &&
(jtag_reset_config & RESET_SRST_NO_GATING)) {
adapter_assert_reset();
@ -1101,7 +1113,8 @@ static int cortex_m_deassert_reset(struct target *target)
enum reset_types jtag_reset_config = jtag_get_reset_config();
if ((jtag_reset_config & RESET_HAS_SRST) &&
!(jtag_reset_config & RESET_SRST_NO_GATING)) {
!(jtag_reset_config & RESET_SRST_NO_GATING) &&
target_was_examined(target)) {
int retval = dap_dp_init(armv7m->debug_ap->dap);
if (retval != ERROR_OK) {
LOG_ERROR("DP initialisation failed");