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riscv-openocd/tcl/board/pxa255_sst.cfg

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- add missing svn props from svn 1798 commit git-svn-id: svn://svn.berlios.de/openocd/trunk@1808 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-05-18 02:04:58 -05:00
# A PXA255 test board with SST 39LF400A flash
#
# At reset the memory map is as follows. Note that
Remove annoying end-of-line whitespace from tcl/* files git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-09-21 13:48:22 -05:00
# the memory map changes later on as the application
- add missing svn props from svn 1798 commit git-svn-id: svn://svn.berlios.de/openocd/trunk@1808 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-05-18 02:04:58 -05:00
# starts...
#
# RAM at 0x4000000
# Flash at 0x00000000
#
source [find target/pxa255.cfg]
David Brownell <david-b@pacbell.net>: Improve the PXA255 target config: move all that board-specific setup to the pxa255_sst board.cfg, to which it evidently belongs (it's the only PXA255 board now included). Provide the PXA255 JTAG id from Intel docs, and add a comment about how this chip is now EOL'd (last orders taken). Note that I still can't get my old PXA255 board to work. There's something broken in the reset sequence, which is preventing the TAP from coming up at all. Old mailing list posts suggest this is a longstanding bug... git-svn-id: svn://svn.berlios.de/openocd/trunk@2416 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-29 15:04:08 -05:00
- add missing svn props from svn 1798 commit git-svn-id: svn://svn.berlios.de/openocd/trunk@1808 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-05-18 02:04:58 -05:00
# Target name is set by above
target.cfg: remove "-work-area-virt 0" The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-08 10:52:40 -06:00
$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
- add missing svn props from svn 1798 commit git-svn-id: svn://svn.berlios.de/openocd/trunk@1808 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-05-18 02:04:58 -05:00
David Brownell <david-b@pacbell.net>: Improve the PXA255 target config: move all that board-specific setup to the pxa255_sst board.cfg, to which it evidently belongs (it's the only PXA255 board now included). Provide the PXA255 JTAG id from Intel docs, and add a comment about how this chip is now EOL'd (last orders taken). Note that I still can't get my old PXA255 board to work. There's something broken in the reset sequence, which is preventing the TAP from coming up at all. Old mailing list posts suggest this is a longstanding bug... git-svn-id: svn://svn.berlios.de/openocd/trunk@2416 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-29 15:04:08 -05:00
# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
proc pxa255_sst_init {} {
xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
#
# setup GPIO
#
mww 0x40E00018 0x00008000 #CPSR0
sleep 20
mww 0x40E0001C 0x00000002 #GPSR1
sleep 20
mww 0x40E00020 0x00000008 #GPSR2
sleep 20
mww 0x40E0000C 0x00008000 #GPDR0
sleep 20
mww 0x40E00054 0x80000000 #GAFR0_L
sleep 20
mww 0x40E00058 0x00188010 #GAFR0_H
sleep 20
mww 0x40E0005C 0x60908018 #GAFR1_L
sleep 20
mww 0x40E0000C 0x0280E000 #GPDR0
sleep 20
mww 0x40E00010 0x821C88B2 #GPDR1
sleep 20
mww 0x40E00014 0x000F03DB #GPDR2
sleep 20
mww 0x40E00000 0x000F03DB #GPLR0
sleep 20
mww 0x40F00004 0x00000020 #PSSR
sleep 20
#
# setup memory controller
#
mww 0x48000008 0x01111998 #MSC0
sleep 20
mww 0x48000010 0x00047ff0 #MSC2
sleep 20
mww 0x48000014 0x00000000 #MECR
sleep 20
mww 0x48000028 0x00010504 #MCMEM0
sleep 20
mww 0x4800002C 0x00010504 #MCMEM1
sleep 20
mww 0x48000030 0x00010504 #MCATT0
sleep 20
mww 0x48000034 0x00010504 #MCATT1
sleep 20
mww 0x48000038 0x00004715 #MCIO0
sleep 20
mww 0x4800003C 0x00004715 #MCIO1
sleep 20
#
mww 0x48000004 0x03CA4018 #MDREF
sleep 20
mww 0x48000004 0x004B4018 #MDREF
sleep 20
mww 0x48000004 0x000B4018 #MDREF
sleep 20
mww 0x48000004 0x000BC018 #MDREF
sleep 20
mww 0x48000000 0x00001AC8 #MDCNFG
sleep 20
sleep 20
mww 0x48000000 0x00001AC9 #MDCNFG
sleep 20
mww 0x48000040 0x00000000 #MDMRS
sleep 20
}
$_TARGETNAME configure -event reset-init {pxa255_sst_init}
reset_config trst_and_srst
jtag_nsrst_delay 200
jtag_ntrst_delay 200
#xscale debug_handler 0 0xFFFF0800 # debug handler base address