riscv-openocd/tcl/target/hi6220.cfg

# Hisilicon Hi6220 Target

if { [info exists CHIPNAME] } {
  set _CHIPNAME $CHIPNAME
} else {
  set _CHIPNAME hi6220
}

#
# Main DAP
#
if { [info exists DAP_TAPID] } {
   set _DAP_TAPID $DAP_TAPID
} else {
   set _DAP_TAPID 0x4ba00477
}

# declare the one JTAG tap to access the DAP
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version

# create the DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap

# declare the 8 main application cores
set _TARGETNAME $_CHIPNAME.cpu
set _smp_command ""

set $_TARGETNAME.cti(0) 0x80198000
set $_TARGETNAME.cti(1) 0x80199000
set $_TARGETNAME.cti(2) 0x8019A000
set $_TARGETNAME.cti(3) 0x8019B000
set $_TARGETNAME.cti(4) 0x801D8000
set $_TARGETNAME.cti(5) 0x801D9000
set $_TARGETNAME.cti(6) 0x801DA000
set $_TARGETNAME.cti(7) 0x801DB000

set _cores 8
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {

    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0

    set _command "target create ${_TARGETNAME}$_core aarch64 \
                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"

    if { $_core != 0 } {
        # non-boot core examination may fail
        set _command "$_command -defer-examine"
        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
    } else {
        # uncomment when "hawt" rtos is merged
        # set _command "$_command -rtos hawt"
        set _smp_command "target smp ${_TARGETNAME}$_core"
    }

    eval $_command
}

eval $_smp_command

cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80003000

# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine

# declare the auxiliary Cortex-A7 core
target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine