riscv-openocd/tcl/target/rp2040-core0.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

transport select swd

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME rp2040
}

if { [info exists WORKAREASIZE] } {
	set _WORKAREASIZE $WORKAREASIZE
} else {
	set _WORKAREASIZE 0x10000
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	set _CPUTAPID 0x01002927
}

swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap

# Backup the work area. The flash probe runs an algorithm on the target CPU.
# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1

set _FLASHNAME $_CHIPNAME.flash
set _FLASHSIZE 0x200000
set _FLASHBASE 0x10000000
flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME

# srst does not exist; use SYSRESETREQ to perform a soft reset
cortex_m reset_config sysresetreq