riscv-openocd/tcl/target/imx35.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# imx35 config
#

reset_config trst_and_srst srst_gates_jtag
jtag_ntrst_delay 100

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME imx35
}

if { [info exists ENDIAN] } {
   set _ENDIAN $ENDIAN
} else {
   set _ENDIAN little
}

if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x07b3601d
}

if { [info exists SDMATAPID] } {
   set _SDMATAPID $SDMATAPID
} else {
   set _SDMATAPID 0x0882601d
}

if { [info exists ETBTAPID] } {
   set _ETBTAPID $ETBTAPID
} else {
   set _ETBTAPID 0x2b900f0f
}

#========================================

jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID

# No IDCODE for this TAP
jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0

jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME

proc power_restore {} { echo "Sensed power restore. No action." }
proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }

# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb