2022-06-12 16:42:27 -05:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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2014-03-21 11:43:04 -05:00
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# Xilinx Zynq-7000 All Programmable SoC
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#
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# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
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2022-11-29 20:42:18 -06:00
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# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip
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2014-03-21 11:43:04 -05:00
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#
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2022-11-29 20:42:18 -06:00
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# 0x03736093 XQ7Z100 XC7Z100I XC7Z100
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# 0x03731093 XQ7Z045 XC7Z045I XC7Z045
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# 0x0372c093 XQ7Z030 XC7Z030I XC7Z030 XA7Z030
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# 0x03727093 XQ7Z020 XC7Z020I XC7Z020 XA7Z020
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# 0x03732093 XC7Z035I XC7Z035
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# 0x0373b093 XC7Z015I XC7Z015
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# 0x03728093 XC7Z014S
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# 0x0373c093 XC7Z012S
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# 0x03722093 XC7Z010I XC7Z010 XA7Z010
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# 0x03723093 XC7Z007S
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2014-03-21 11:43:04 -05:00
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set _CHIPNAME zynq
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set _TARGETNAME $_CHIPNAME.cpu
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2022-11-29 20:42:18 -06:00
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jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \
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-expected-id 0x03723093 \
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-expected-id 0x03722093 \
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-expected-id 0x0373c093 \
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-expected-id 0x03728093 \
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-expected-id 0x0373B093 \
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-expected-id 0x03732093 \
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2017-06-30 13:54:38 -05:00
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-expected-id 0x03727093 \
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2022-11-29 20:42:18 -06:00
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-expected-id 0x0372C093 \
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-expected-id 0x03731093 \
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2017-06-30 13:54:38 -05:00
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-expected-id 0x03736093
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2014-03-21 11:43:04 -05:00
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2018-03-23 15:17:29 -05:00
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
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2014-03-21 11:43:04 -05:00
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2018-03-23 15:17:29 -05:00
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
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2014-03-21 11:43:04 -05:00
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-coreid 0 -dbgbase 0x80090000
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2018-03-23 15:17:29 -05:00
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target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
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2014-03-21 11:43:04 -05:00
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-coreid 1 -dbgbase 0x80092000
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target smp ${_TARGETNAME}0 ${_TARGETNAME}1
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2019-08-23 08:51:00 -05:00
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adapter speed 1000
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2014-03-21 11:43:04 -05:00
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${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
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${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
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2017-07-05 13:48:34 -05:00
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2023-06-03 13:16:19 -05:00
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pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
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2022-11-16 19:01:04 -06:00
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virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23
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2017-07-05 13:48:34 -05:00
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc zynqpl_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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