riscv-openocd/tcl/target/zynq_7000.cfg

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# SPDX-License-Identifier: GPL-2.0-or-later
# Xilinx Zynq-7000 All Programmable SoC
#
# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip
#
# 0x03736093 XQ7Z100 XC7Z100I XC7Z100
# 0x03731093 XQ7Z045 XC7Z045I XC7Z045
# 0x0372c093 XQ7Z030 XC7Z030I XC7Z030 XA7Z030
# 0x03727093 XQ7Z020 XC7Z020I XC7Z020 XA7Z020
# 0x03732093 XC7Z035I XC7Z035
# 0x0373b093 XC7Z015I XC7Z015
# 0x03728093 XC7Z014S
# 0x0373c093 XC7Z012S
# 0x03722093 XC7Z010I XC7Z010 XA7Z010
# 0x03723093 XC7Z007S
set _CHIPNAME zynq
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \
-expected-id 0x03723093 \
-expected-id 0x03722093 \
-expected-id 0x0373c093 \
-expected-id 0x03728093 \
-expected-id 0x0373B093 \
-expected-id 0x03732093 \
-expected-id 0x03727093 \
-expected-id 0x0372C093 \
-expected-id 0x03731093 \
-expected-id 0x03736093
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80090000
target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
-coreid 1 -dbgbase 0x80092000
target smp ${_TARGETNAME}0 ${_TARGETNAME}1
adapter speed 1000
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23
set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b
set XC7_JSTART 0x0c
set XC7_BYPASS 0x3f
proc zynqpl_program {tap} {
global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
irscan $tap $XC7_JSHUTDOWN
irscan $tap $XC7_JPROGRAM
runtest 60000
#JSTART prevents this from working...
#irscan $tap $XC7_JSTART
runtest 2000
irscan $tap $XC7_BYPASS
runtest 2000
}