interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
riscv-openocd/src/target/arm946e.c

793 lines
23 KiB
C
Raw Normal View History

arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2010 by Drasko DRASKOVIC *
* drasko.draskovic@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
Remove FSF address from GPL notices Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-16 15:41:00 -05:00
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
***************************************************************************/
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "arm946e.h"
#include "target_type.h"
#include "arm_opcodes.h"
#include "breakpoints.h"
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
#define NB_CACHE_WAYS 4
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
#define CP15_CTL 0x02
#define CP15_CTL_DCACHE (1<<2)
#define CP15_CTL_ICACHE (1<<12)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/**
* flag to give info about cache manipulation during debug :
* "0" - cache lines are invalidated "on the fly", for affected addresses.
target: fix minor typos and duplicated words Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-07-12 13:25:00 -05:00
* This is preferred from performance point of view.
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
* "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
* It is kept off during debugging.
*/
static uint8_t arm946e_preserve_cache;
int arm946e_post_debug_entry(struct target *target);
void arm946e_pre_restore_context(struct target *target);
static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
int arm946e_init_arch_info(struct target *target,
struct arm946e_common *arm946e,
struct jtag_tap *tap)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
struct arm7_9_common *arm7_9 = &arm946e->arm7_9_common;
/* initialize arm7/arm9 specific info (including armv4_5) */
arm9tdmi_init_arch_info(target, arm7_9, tap);
arm946e->common_magic = ARM946E_COMMON_MAGIC;
/**
* The ARM946E-S implements the ARMv5TE architecture which
* has the BKPT instruction, so we don't have to use a watchpoint comparator
*/
arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
arm7_9->post_debug_entry = arm946e_post_debug_entry;
arm7_9->pre_restore_context = arm946e_pre_restore_context;
/**
* disabling linefills leads to lockups, so keep them enabled for now
* this doesn't affect correctness, but might affect timing issues, if
* important data is evicted from the cache during the debug session
*/
arm946e_preserve_cache = 0;
/* override hw single-step capability from ARM9TDMI */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
/* arm7_9->has_single_step = 1; */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return ERROR_OK;
}
static int arm946e_target_create(struct target *target, Jim_Interp *interp)
{
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
struct arm946e_common *arm946e = calloc(1, sizeof(struct arm946e_common));
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
arm946e_init_arch_info(target, arm946e, target->tap);
return ERROR_OK;
}
target: fix memory leaks on targets based on arm9tdmi Similarly to the fix for arm926ejs (also base on arm9tdmi), fix the other targets based on arm9tdmi. The fix for arm926ejs is tested on SPEAr320 target. This fix is proposed separately because is not tested on a correct target device, but tested on SPEAr320 by hacking the target type and pretending it is the correct one, e.g.: sed -i s/arm926ejs/arm920t/ tcl/target/spear3xx.cfg The memory leaks detected and fixed are: - arm register cache; - EmbeddedICE register cache; - arm_jtag_reset_callback internal data; - struct <target_type>_common. Change-Id: I565f9a5bf144a9df78474434d86a64127ef0fbe5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5699 Tested-by: jenkins
2020-05-25 04:28:22 -05:00
static void arm946e_deinit_target(struct target *target)
{
struct arm *arm = target_to_arm(target);
struct arm946e_common *arm946e = target_to_arm946(target);
arm7_9_deinit(target);
arm_free_reg_cache(arm);
free(arm946e);
}
target/arm946e: change prototype of arm946e_verify_pointer() To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of arm946e_verify_pointer() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: Ib7119e2b009d05eec47b50c3b9d32feaebc97538 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5060 Tested-by: jenkins
2019-03-31 21:46:29 -05:00
static int arm946e_verify_pointer(struct command_invocation *cmd,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
struct arm946e_common *arm946e)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(cmd, "target is not an ARM946");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
}
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
/*
* Update cp15_control_reg, saved on debug_entry.
*/
static void arm946e_update_cp15_caches(struct target *target, uint32_t value)
{
struct arm946e_common *arm946e = target_to_arm946(target);
arm946e->cp15_control_reg = (arm946e->cp15_control_reg & ~(CP15_CTL_DCACHE|CP15_CTL_ICACHE))
| (value & (CP15_CTL_DCACHE|CP15_CTL_ICACHE));
}
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/*
* REVISIT: The "read_cp15" and "write_cp15" commands could hook up
* to eventual mrc() and mcr() routines ... the reg_addr values being
* constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
* See section 7.3 of the ARM946E-S TRM.
*/
static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
target/arm: Remove usage of struct arm_jtag in ARMv7 targets The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-11-13 17:30:28 -06:00
retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
if (retval != ERROR_OK)
return retval;
fields[0].num_bits = 32;
/* REVISIT: table 7-2 shows that bits 31-31 need to be
* specified for accessing BIST registers ...
*/
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].num_bits = 6;
fields[1].out_value = &reg_addr_buf;
fields[1].in_value = NULL;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
fields[0].in_value = (uint8_t *)value;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
retval = jtag_execute_queue();
if (retval != ERROR_OK)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
return ERROR_OK;
}
int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 1;
uint8_t value_buf[4];
buf_set_u32(value_buf, 0, 32, value);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
target/arm: Remove usage of struct arm_jtag in ARMv7 targets The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-11-13 17:30:28 -06:00
retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
if (retval != ERROR_OK)
return retval;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].in_value = NULL;
fields[1].num_bits = 6;
fields[1].out_value = &reg_addr_buf;
fields[1].in_value = NULL;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
#endif
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
retval = jtag_execute_queue();
if (retval != ERROR_OK)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
return ERROR_OK;
}
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
#define GET_ICACHE_SIZE 6
#define GET_DCACHE_SIZE 18
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
/*
* \param target struct target pointer
* \param idsel select GET_ICACHE_SIZE or GET_DCACHE_SIZE
* \returns cache size, given in bytes
*/
static uint32_t arm946e_cp15_get_csize(struct target *target, int idsel)
{
struct arm946e_common *arm946e = target_to_arm946(target);
uint32_t csize = arm946e->cp15_cache_info;
if (csize == 0) {
if (arm946e_read_cp15(target, 0x01, &csize) == ERROR_OK)
arm946e->cp15_cache_info = csize;
}
if (csize & (1<<(idsel-4))) /* cache absent */
return 0;
csize = (csize >> idsel) & 0x0F;
return csize ? 1 << (12 + (csize-3)) : 0;
}
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
uint32_t arm946e_invalidate_whole_dcache(struct target *target)
{
uint32_t csize = arm946e_cp15_get_csize(target, GET_DCACHE_SIZE);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
if (csize == 0)
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
/* One line (index) is 32 bytes (8 words) long, 4-way assoc
* ARM DDI 0201D, Section 3.3.5
*/
int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
target: fix minor typos and duplicated words Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-07-12 13:25:00 -05:00
/* Loop for all segments (i.e. ways) */
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
uint32_t seg;
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Loop for all indexes */
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
int idx;
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
for (idx = 0; idx < nb_idx; idx++) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Form and write cp15 index (segment + line idx) */
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
uint32_t cp15_idx = seg << 30 | idx << 5;
int retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR writing index");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
/* Read dtag */
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
uint32_t dtag;
target/arm946e: add missing error detection Discoverd by clang static analyzer. While on it remove useless type casts from arm946e_read_cp15() parameter. Change-Id: I549e19685b431400243800ee0f7d1bbe6cdb14b4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5376 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-12-20 16:43:55 -06:00
retval = arm946e_read_cp15(target, 0x16, &dtag);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR reading dtag");
return retval;
}
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Check cache line VALID bit */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (!(dtag >> 4 & 0x1))
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
continue;
/* Clean data cache line */
retval = arm946e_write_cp15(target, 0x35, 0x1);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR cleaning cache line");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
/* Flush data cache line */
retval = arm946e_write_cp15(target, 0x1a, 0x1);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR flushing cache line");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
}
}
return ERROR_OK;
}
uint32_t arm946e_invalidate_whole_icache(struct target *target)
{
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
/* Check cache presence before flushing - avoid undefined behavior */
uint32_t csize = arm946e_cp15_get_csize(target, GET_ICACHE_SIZE);
if (csize == 0)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
LOG_DEBUG("FLUSHING I$");
/**
* Invalidate (flush) I$
* mcr 15, 0, r0, cr7, cr5, {0}
*/
arm946e: cleanup C0.C cache type reg access Cache type register C0.C is read-only, and display hard core configuration information. This information is unlikely be changed in runtime. - removed C0.C access when result is not used in arm946e_invalidate_dcache() - access C0.C only once per target, store result in cp15_cache_info field of target structure - fix cache index count calculation Change-Id: I12bc4c967fdf07f54d755f2f2f42406c0ababc1a Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/693 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:18:04 -05:00
int retval = arm946e_write_cp15(target, 0x0f, 0x1);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR flushing I$");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
return ERROR_OK;
}
int arm946e_post_debug_entry(struct target *target)
{
uint32_t ctr_reg = 0x0;
uint32_t retval = ERROR_OK;
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
struct arm946e_common *arm946e = target_to_arm946(target);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* See if CACHES are enabled, and save that info
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
* in the context bits, so that arm946e_pre_restore_context() can use them */
target/arm946e: add missing error detection Discoverd by clang static analyzer. While on it remove useless type casts from arm946e_read_cp15() parameter. Change-Id: I549e19685b431400243800ee0f7d1bbe6cdb14b4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5376 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-12-20 16:43:55 -06:00
arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
/* Save control reg in the context */
arm946e->cp15_control_reg = ctr_reg;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (arm946e_preserve_cache) {
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
if (ctr_reg & CP15_CTL_DCACHE) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Clean and flush D$ */
arm946e_invalidate_whole_dcache(target);
/* Disable D$ */
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
ctr_reg &= ~CP15_CTL_DCACHE;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
if (ctr_reg & CP15_CTL_ICACHE) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Flush I$ */
arm946e_invalidate_whole_icache(target);
/* Disable I$ */
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
ctr_reg &= ~CP15_CTL_ICACHE;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
/* Write the new configuration */
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
retval = arm946e_write_cp15(target, CP15_CTL, ctr_reg);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
LOG_DEBUG("ERROR disabling cache");
return retval;
}
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
} /* if preserve_cache */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return ERROR_OK;
}
void arm946e_pre_restore_context(struct target *target)
{
uint32_t ctr_reg = 0x0;
uint32_t retval;
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (arm946e_preserve_cache) {
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
struct arm946e_common *arm946e = target_to_arm946(target);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Get the contents of the CTR reg */
target/arm946e: add missing error detection Discoverd by clang static analyzer. While on it remove useless type casts from arm946e_read_cp15() parameter. Change-Id: I549e19685b431400243800ee0f7d1bbe6cdb14b4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5376 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-12-20 16:43:55 -06:00
arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/**
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
* Read-modify-write CP15 control
* to reenable I/D-cache operation
* NOTE: It is not possible to disable cache by CP15.
* if arm946e_preserve_cache debugging flag enabled.
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
*/
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
ctr_reg |= arm946e->cp15_control_reg & (CP15_CTL_DCACHE|CP15_CTL_ICACHE);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Write the new configuration */
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
retval = arm946e_write_cp15(target, CP15_CTL, ctr_reg);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
if (retval != ERROR_OK)
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR enabling cache");
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
} /* if preserve_cache */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
uint32_t size, uint32_t count)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
uint32_t cur_addr = 0x0;
uint32_t cp15_idx, set, way, dtag;
uint32_t i = 0;
int retval;
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
for (i = 0; i < count*size; i++) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
cur_addr = address + i;
set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
for (way = 0; way < NB_CACHE_WAYS; way++) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/**
* Find if the affected address is kept in the cache.
* Because JTAG Scan Chain 15 offers limited approach,
* we have to loop through all cache ways (segments) and
* read cache tags, then compare them with with address.
*/
/* Form and write cp15 index (segment + line idx) */
cp15_idx = way << 30 | set << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR writing index");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
/* Read dtag */
target/arm946e: add missing error detection Discoverd by clang static analyzer. While on it remove useless type casts from arm946e_read_cp15() parameter. Change-Id: I549e19685b431400243800ee0f7d1bbe6cdb14b4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5376 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-12-20 16:43:55 -06:00
retval = arm946e_read_cp15(target, 0x16, &dtag);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR reading dtag");
return retval;
}
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Check cache line VALID bit */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (!(dtag >> 4 & 0x1))
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
continue;
/* If line is valid and corresponds to affected address - invalidate it */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (dtag >> 5 == cur_addr >> 5) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Clean data cache line */
retval = arm946e_write_cp15(target, 0x35, 0x1);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR cleaning cache line");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
/* Flush data cache line */
retval = arm946e_write_cp15(target, 0x1c, 0x1);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR flushing cache line");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
break;
}
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
} /* loop through all 4 ways */
} /* loop through all addresses */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return ERROR_OK;
}
uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
uint32_t size, uint32_t count)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
uint32_t cur_addr = 0x0;
uint32_t cp15_idx, set, way, itag;
uint32_t i = 0;
int retval;
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
for (i = 0; i < count*size; i++) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
cur_addr = address + i;
set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
for (way = 0; way < NB_CACHE_WAYS; way++) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Form and write cp15 index (segment + line idx) */
cp15_idx = way << 30 | set << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR writing index");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
/* Read itag */
target/arm946e: add missing error detection Discoverd by clang static analyzer. While on it remove useless type casts from arm946e_read_cp15() parameter. Change-Id: I549e19685b431400243800ee0f7d1bbe6cdb14b4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5376 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-12-20 16:43:55 -06:00
retval = arm946e_read_cp15(target, 0x17, &itag);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR reading itag");
return retval;
}
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Check cache line VALID bit */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (!(itag >> 4 & 0x1))
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
continue;
/* If line is valid and corresponds to affected address - invalidate it */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (itag >> 5 == cur_addr >> 5) {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Flush I$ line */
retval = arm946e_write_cp15(target, 0x1d, 0x0);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK) {
nit: more LOG_* \n fixes Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages Remove LOG_INFO_N LOG_INFO_N was only used once and had a \n at the end Change LOG_USER_N calls that end with \n to LOG_USER
2011-01-05 20:54:12 -06:00
LOG_DEBUG("ERROR flushing cache line");
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
}
break;
}
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
} /* way loop */
} /* addr loop */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return ERROR_OK;
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
target: Add 64-bit target address support Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2013-09-23 03:27:03 -05:00
int arm946e_write_memory(struct target *target, target_addr_t address,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
uint32_t size, uint32_t count, const uint8_t *buffer)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
int retval;
LOG_DEBUG("-");
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
struct arm946e_common *arm946e = target_to_arm946(target);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
/* Invalidate D$ if it is ON */
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
if (!arm946e_preserve_cache && (arm946e->cp15_control_reg & CP15_CTL_DCACHE))
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
arm946e_invalidate_dcache(target, address, size, count);
/**
* Write memory
*/
[RFC] target: Move bulk_write_memory to arm7_9 The only remaining user is arm7_9 so remove it from the target API and add it to struct arm7_9_common to support all its variants with minimal changes. Many of the variants are likely not correct in the cache/mmu handling when the bulk write is triggered. This patch does nothing to change that, except for arm946e, where it was easier to do what might be the right thing. Change-Id: Ie73ac07507ff0936fefdb90760046cc8810ed182 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1220 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-11 16:21:13 -05:00
retval = arm7_9_write_memory_opt(target, address, size, count, buffer);
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (retval != ERROR_OK)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
/* *
* Invalidate I$ if it is ON.
*
* D$ has been cleaned and flushed before mem write thus forcing it to behave like write-through,
* because arm7_9_write_memory() has seen non-valid bit in D$
* and wrote data into physical RAM (without touching or allocating the cache line).
* From ARM946ES Technical Reference Manual we can see that it uses "allocate on read-miss"
* policy for both I$ and D$ (Chapter 3.2 and 3.3)
*
* Explanation :
* "ARM system developer's guide: designing and optimizing system software" by
* Andrew N. Sloss, Dominic Symes and Chris Wright,
* Chapter 12.3.3 Allocating Policy on a Cache Miss :
* A read allocate on cache miss policy allocates a cache line only during a read from main memory.
* If the victim cache line contains valid data, then it is written to main memory before the cache line
* is filled with new data.
* Under this strategy, a write of new data to memory does not update the contents of the cache memory
* unless a cache line was allocated on a previous read from main memory.
* If the cache line contains valid data, then the write updates the cache and may update the main memory if
* the cache write policy is write-through.
* If the data is not in the cache, the controller writes to main memory only.
*/
arm946e: don't use global variables for context Global variables 'dc' 'ic' had been used in the code to keep target's state of D-cache and I-cache on debug entry. This may lead to incorrect operation in configurations with multiple cores and unequal cache states. Fix: move cache state to the appropriate bits of the 'cp15_control_reg' field (already present but unused). Vaule of cp15 control register stored here on arm946e_post_debug_entry(), and analyzed later in arm946e_write_memory(). Change-Id: I71ef82be00c21d6fffb3726cec4974d1ece70dfe Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/692 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-07-30 18:50:09 -05:00
if (!arm946e_preserve_cache && (arm946e->cp15_control_reg & CP15_CTL_ICACHE))
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
arm946e_invalidate_icache(target, address, size, count);
return ERROR_OK;
}
target: Add 64-bit target address support Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2013-09-23 03:27:03 -05:00
int arm946e_read_memory(struct target *target, target_addr_t address,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
uint32_t size, uint32_t count, uint8_t *buffer)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
int retval;
LOG_DEBUG("-");
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
retval = arm7_9_read_memory(target, address, size, count, buffer);
if (retval != ERROR_OK)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
return retval;
return ERROR_OK;
}
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
COMMAND_HANDLER(arm946e_handle_cp15)
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
{
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
/* one or two arguments, access a single register (write if second argument is given) */
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
if (CMD_ARGC < 1 || CMD_ARGC > 2)
return ERROR_COMMAND_SYNTAX_ERROR;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
struct target *target = get_current_target(CMD_CTX);
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
struct arm946e_common *arm946e = target_to_arm946(target);
target/arm946e: change prototype of arm946e_verify_pointer() To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of arm946e_verify_pointer() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: Ib7119e2b009d05eec47b50c3b9d32feaebc97538 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5060 Tested-by: jenkins
2019-03-31 21:46:29 -05:00
int retval = arm946e_verify_pointer(CMD, arm946e);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
if (retval != ERROR_OK)
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
return retval;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
if (target->state != TARGET_HALTED) {
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
return ERROR_TARGET_NOT_HALTED;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
uint32_t address;
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
if (CMD_ARGC == 1) {
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
uint32_t value;
retval = arm946e_read_cp15(target, address, &value);
if (retval != ERROR_OK) {
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
return retval;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
retval = jtag_execute_queue();
if (retval != ERROR_OK)
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
return retval;
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
/* Return value in hex format */
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "0x%08" PRIx32, value);
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
} else if (CMD_ARGC == 2) {
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
uint32_t value;
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
retval = arm946e_write_cp15(target, address, value);
if (retval != ERROR_OK) {
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
return retval;
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
}
if (address == CP15_CTL)
arm946e_update_cp15_caches(target, value);
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
return ERROR_OK;
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
}
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
COMMAND_HANDLER(arm946e_handle_idcache)
{
if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm946e_common *arm946e = target_to_arm946(target);
target/arm946e: change prototype of arm946e_verify_pointer() To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of arm946e_verify_pointer() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: Ib7119e2b009d05eec47b50c3b9d32feaebc97538 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5060 Tested-by: jenkins
2019-03-31 21:46:29 -05:00
retval = arm946e_verify_pointer(CMD, arm946e);
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
return ERROR_TARGET_NOT_HALTED;
}
bool icache = (strcmp(CMD_NAME, "icache") == 0);
uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024;
if (CMD_ARGC == 0) {
bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
&& (arm946e->cp15_control_reg & 0x1);
if (csize == 0)
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "%s-cache absent", icache ? "I" : "D");
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
else
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "%s-cache size: %" PRIu32 "K, %s",
Clean up many C99 integer types format specifiers This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-30 04:31:57 -05:00
icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
return ERROR_OK;
}
bool flush = false;
bool enable = false;
retval = command_parse_bool_arg(CMD_ARGV[0], &enable);
if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
if (strcmp(CMD_ARGV[0], "flush") == 0) {
flush = true;
retval = ERROR_OK;
} else
return retval;
}
/* Do not invalidate or change state, if cache is absent */
if (csize == 0) {
helper/command: change prototype of command_print/command_print_sameline To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-03 03:37:24 -05:00
command_print(CMD, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* NOTE: flushing entire cache will not preserve lock-down cache regions */
if (icache) {
if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable)
retval = arm946e_invalidate_whole_icache(target);
} else {
if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable)
retval = arm946e_invalidate_whole_dcache(target);
}
if (retval != ERROR_OK || flush)
return retval;
uint32_t value;
retval = arm946e_read_cp15(target, CP15_CTL, &value);
if (retval != ERROR_OK)
return retval;
uint32_t vnew = value;
uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE;
if (enable) {
if ((value & 0x1) == 0)
LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
vnew |= cmask;
} else
vnew &= ~cmask;
if (vnew == value)
return ERROR_OK;
retval = arm946e_write_cp15(target, CP15_CTL, vnew);
if (retval != ERROR_OK)
return retval;
arm946e_update_cp15_caches(target, vnew);
return ERROR_OK;
}
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
static const struct command_registration arm946e_exec_command_handlers[] = {
{
.name = "cp15",
target/arm946e: rewrite jim_arm946e_cp15 to arm945e_handle_cp15 jim_arm946e_cp15() used command_print() in the jim handler. Change-Id: I0a258aad5a60f45672b9b6fa6819691507d4f0f6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5000 Tested-by: jenkins
2019-03-26 05:55:37 -05:00
.handler = arm946e_handle_cp15,
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.mode = COMMAND_EXEC,
.usage = "regnum [value]",
arm946e: cp15 command returns value to the script Not just print it. This enables scripts to analyze valuable config options of arm946e-s cores, do internal BIST memory tests and more. Be careful to flush caches before disabling it. Do not forget that BIST test overwrites memory. - cp15 rewritten from COMMAND_HANDLER to jim_handler. Change-Id: I734da0be6db0a3127c2daa94ed75efef94da8ceb Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/694 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:21:31 -05:00
.help = "read/modify cp15 register",
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
},
arm946e: add icache/dcache manipulation commands. Provide cache operations coherent with internal target state. Functions similar to xscale target. Change-Id: Ic6b9a894154f6e4f5672b5d7f5035c9774ee9499 Signed-off-by: Alexander Osipenko <sipych@gmail.com> Reviewed-on: http://openocd.zylin.com/695 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-06-08 14:24:13 -05:00
{
.name = "icache",
.handler = arm946e_handle_idcache,
.mode = COMMAND_EXEC,
.usage = "['enable'|'disable'|'flush']",
.help = "I-cache info and operations",
},
{
.name = "dcache",
.handler = arm946e_handle_idcache,
.mode = COMMAND_EXEC,
.usage = "['enable'|'disable'|'flush']",
.help = "D-cache info and operations",
},
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
COMMAND_REGISTRATION_DONE
};
const struct command_registration arm946e_command_handlers[] = {
{
.chain = arm9tdmi_command_handlers,
},
{
.name = "arm946e",
.mode = COMMAND_ANY,
.help = "arm946e command group",
cmd: add missing usage vars we should have caught them all - hopefully. Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/381 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-16 07:35:23 -06:00
.usage = "",
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.chain = arm946e_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
/** Holds methods for ARM946 targets. */
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
struct target_type arm946e_target = {
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.name = "arm946e",
.poll = arm7_9_poll,
.arch_state = arm_arch_state,
.target_request_data = arm7_9_target_request_data,
.halt = arm7_9_halt,
.resume = arm7_9_resume,
.step = arm7_9_step,
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
target/arm: add support for multi-architecture gdb GDB can be built for multi-architecture through the command ./configure --enable-targets=all && make Such multi-architecture GDB requires the target's architecture to be selected either manually by the user through the GDB command "set architecture" or automatically by the target description sent by the remote target (i.e. OpenOCD). Commit e65acd889c61a424c7bd72fdee5d6a3aee1d8504 ("gdb_server: add support for architecture element") already provides the required infrastructure to support multi-architecture gdb. arm-none-eabi-gdb 8.2 uses "arm" as default architecture, but also supports the following values: "arm_any", "armv2", "armv2a", "armv3", "armv3m", "armv4", "armv4t", "armv5", "armv5t", "armv5te", "armv5tej", "armv6", "armv6k", "armv6kz", "armv6-m", "armv6s-m", "armv6t2", "armv7", "armv7e-m", "armv8-a", "armv8-m.base", "armv8-m.main", "armv8-r", "ep9312", "iwmmxt", "iwmmxt2", "xscale". These values can be displayed on arm gdb prompt by typing "set architecture " followed by a TAB for autocompletion. Set the gdb architecture value for all arm targets to "arm". Change-Id: I176cb89878606e1febd546ce26543b3e7849500a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4754 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-11-01 08:50:27 -05:00
.get_gdb_arch = arm_get_gdb_arch,
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.get_gdb_reg_list = arm_get_gdb_reg_list,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
/* .read_memory = arm7_9_read_memory, */
/* .write_memory = arm7_9_write_memory, */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.read_memory = arm946e_read_memory,
.write_memory = arm946e_write_memory,
.checksum_memory = arm_checksum_memory,
.blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
build: cleanup src/target directory Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-02-05 06:03:04 -06:00
/* .add_breakpoint = arm946e_add_breakpoint, */
/* .remove_breakpoint = arm946e_remove_breakpoint, */
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
.commands = arm946e_command_handlers,
.target_create = arm946e_target_create,
.init_target = arm9tdmi_init_target,
target: fix memory leaks on targets based on arm9tdmi Similarly to the fix for arm926ejs (also base on arm9tdmi), fix the other targets based on arm9tdmi. The fix for arm926ejs is tested on SPEAr320 target. This fix is proposed separately because is not tested on a correct target device, but tested on SPEAr320 by hacking the target type and pretending it is the correct one, e.g.: sed -i s/arm926ejs/arm920t/ tcl/target/spear3xx.cfg The memory leaks detected and fixed are: - arm register cache; - EmbeddedICE register cache; - arm_jtag_reset_callback internal data; - struct <target_type>_common. Change-Id: I565f9a5bf144a9df78474434d86a64127ef0fbe5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5699 Tested-by: jenkins
2020-05-25 04:28:22 -05:00
.deinit_target = arm946e_deinit_target,
arm964e: Add support for ARM946E target. So far most of the people have been using existing ARM966E in the place of ARM946E, because they have practically the same scan chains. However, ARM946E has caches, which further complicates JATG handling via scan-chain. this was preventing single-stepping for ARM946E when SW breakpoints are used. This patch thus introduces : 1) Correct cache handling on memory write 2) Possibility to flush whole cache and turn it off during debug, or just to flush affected lines (faster and better) 3) Correct SW breakpoint handling and correct single-stepping 4) Corrects the bug on CP15 read and write, so CP15 values are now correctly R/W
2010-11-04 08:33:10 -05:00
.examine = arm7_9_examine,
.check_reset = arm7_9_check_reset,
};