riscv-openocd/tcl/target/am437x.cfg

source [find target/icepick.cfg]
source [find mem_helper.tcl]

###############################################################################
##				AM437x Registers			     ##
###############################################################################
set  PRCM_BASE_ADDR                  0x44df0000
set  REVISION_PRM                    [expr       {$PRCM_BASE_ADDR     +  0x0000}]
set  PRM_IRQSTATUS_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0004}]
set  PRM_IRQENABLE_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0008}]
set  PRM_IRQSTATUS_M3                [expr       {$PRCM_BASE_ADDR     +  0x000c}]
set  PRM_IRQENABLE_M3                [expr       {$PRCM_BASE_ADDR     +  0x0010}]
set  PM_MPU_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0300}]
set  PM_MPU_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0304}]
set  RM_MPU_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0314}]
set  RM_MPU_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0324}]
set  PM_GFX_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0400}]
set  PM_GFX_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0404}]
set  RM_GFX_RSTCTRL                  [expr       {$PRCM_BASE_ADDR     +  0x0410}]
set  RM_GFX_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0414}]
set  RM_GFX_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0424}]
set  RM_RTC_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0524}]
set  RM_WKUP_RSTCTRL                 [expr       {$PRCM_BASE_ADDR     +  0x2010}]
set  RM_WKUP_RSTST                   [expr       {$PRCM_BASE_ADDR     +  0x2014}]
set  CM_L3_AON_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x2800}]
set  CM_WKUP_DEBUGSS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2820}]
set  CM_L3S_TSC_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2900}]
set  CM_WKUP_ADC_TSC_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2920}]
set  CM_L4_WKUP_AON_CLKSTCTRL        [expr       {$PRCM_BASE_ADDR     +  0x2a00}]
set  CM_WKUP_L4WKUP_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2a20}]
set  CM_WKUP_WKUP_M3_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a28}]
set  CM_WKUP_SYNCTIMER_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a30}]
set  CM_WKUP_CLKDIV32K_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a38}]
set  CM_WKUP_USBPHY0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a40}]
set  CM_WKUP_USBPHY1_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a48}]
set  CM_WKUP_CLKSTCTRL               [expr       {$PRCM_BASE_ADDR     +  0x2b00}]
set  CM_WKUP_TIMER0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b20}]
set  CM_WKUP_TIMER1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b28}]
set  CM_WKUP_WDT0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b30}]
set  CM_WKUP_WDT1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b38}]
set  CM_WKUP_I2C0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b40}]
set  CM_WKUP_UART0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b48}]
set  CM_WKUP_SMARTREFLEX0_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b50}]
set  CM_WKUP_SMARTREFLEX1_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b58}]
set  CM_WKUP_CONTROL_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2b60}]
set  CM_WKUP_GPIO0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b68}]
set  CM_CLKMODE_DPLL_CORE            [expr       {$PRCM_BASE_ADDR     +  0x2d20}]
set  CM_IDLEST_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d24}]
set  CM_CLKSEL_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d2c}]
set  CM_DIV_M4_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d38}]
set  CM_DIV_M5_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d3c}]
set  CM_DIV_M6_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d40}]
set  CM_SSC_DELTAMSTEP_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d48}]
set  CM_SSC_MODFREQDIV_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d4c}]
set  CM_CLKMODE_DPLL_MPU             [expr       {$PRCM_BASE_ADDR     +  0x2d60}]
set  CM_IDLEST_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d64}]
set  CM_CLKSEL_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d6c}]
set  CM_DIV_M2_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d70}]
set  CM_SSC_DELTAMSTEP_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d88}]
set  CM_SSC_MODFREQDIV_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d8c}]
set  CM_CLKMODE_DPLL_DDR             [expr       {$PRCM_BASE_ADDR     +  0x2da0}]
set  CM_IDLEST_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2da4}]
set  CM_CLKSEL_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2dac}]
set  CM_DIV_M2_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db0}]
set  CM_DIV_M4_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db8}]
set  CM_SSC_DELTAMSTEP_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dc8}]
set  CM_SSC_MODFREQDIV_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dcc}]
set  CM_CLKMODE_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2de0}]
set  CM_IDLEST_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2de4}]
set  CM_CLKSEL_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2dec}]
set  CM_DIV_M2_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2df0}]
set  CM_CLKSEL2_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2e04}]
set  CM_SSC_DELTAMSTEP_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e08}]
set  CM_SSC_MODFREQDIV_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e0c}]
set  CM_CLKDCOLDO_DPLL_PER           [expr       {$PRCM_BASE_ADDR     +  0x2e14}]
set  CM_CLKMODE_DPLL_DISP            [expr       {$PRCM_BASE_ADDR     +  0x2e20}]
set  CM_IDLEST_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e24}]
set  CM_CLKSEL_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e2c}]
set  CM_DIV_M2_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e30}]
set  CM_SSC_DELTAMSTEP_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e48}]
set  CM_SSC_MODFREQDIV_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e4c}]
set  CM_CLKMODE_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e60}]
set  CM_IDLEST_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e64}]
set  CM_CLKSEL_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e6c}]
set  CM_DIV_M2_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e70}]
set  CM_CLKSEL2_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e84}]
set  CM_SSC_DELTAMSTEP_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e88}]
set  CM_SSC_MODFREQDIV_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e8c}]
set  CM_SHADOW_FREQ_CONFIG1          [expr       {$PRCM_BASE_ADDR     +  0x2fa0}]
set  CM_SHADOW_FREQ_CONFIG2          [expr       {$PRCM_BASE_ADDR     +  0x2fa4}]
set  CM_CLKOUT1_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4100}]
set  CM_DLL_CTRL                     [expr       {$PRCM_BASE_ADDR     +  0x4104}]
set  CM_CLKOUT2_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4108}]
set  CLKSEL_TIMER1MS_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4200}]
set  CLKSEL_TIMER2_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4204}]
set  CLKSEL_TIMER3_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4208}]
set  CLKSEL_TIMER4_CLK               [expr       {$PRCM_BASE_ADDR     +  0x420c}]
set  CLKSEL_TIMER5_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4210}]
set  CLKSEL_TIMER6_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4214}]
set  CLKSEL_TIMER7_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4218}]
set  CLKSEL_TIMER8_CLK               [expr       {$PRCM_BASE_ADDR     +  0x421c}]
set  CLKSEL_TIMER9_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4220}]
set  CLKSEL_TIMER10_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4224}]
set  CLKSEL_TIMER11_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4228}]
set  CLKSEL_WDT1_CLK                 [expr       {$PRCM_BASE_ADDR     +  0x422c}]
set  CLKSEL_SYNCTIMER_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4230}]
set  CLKSEL_MAC_CLK                  [expr       {$PRCM_BASE_ADDR     +  0x4234}]
set  CLKSEL_CPTS_RFT_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4238}]
set  CLKSEL_GFX_FCLK                 [expr       {$PRCM_BASE_ADDR     +  0x423c}]
set  CLKSEL_GPIO0_DBCLK              [expr       {$PRCM_BASE_ADDR     +  0x4240}]
set  CLKSEL_LCDC_PIXEL_CLK           [expr       {$PRCM_BASE_ADDR     +  0x4244}]
set  CLKSEL_ICSS_OCP_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4248}]
set  CLKSEL_DLL_AGING_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4250}]
set  CLKSEL_USBPHY32KHZ_GCLK         [expr       {$PRCM_BASE_ADDR     +  0x4260}]
set  CM_MPU_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8300}]
set  CM_MPU_MPU_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8320}]
set  CM_GFX_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8400}]
set  CM_GFX_GFX_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8420}]
set  CM_RTC_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8500}]
set  CM_RTC_RTC_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8520}]
set  CM_PER_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8800}]
set  CM_PER_L3_CLKCTRL               [expr       {$PRCM_BASE_ADDR     +  0x8820}]
set  CM_PER_AES0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8828}]
set  CM_PER_DES_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8830}]
set  CM_PER_CRYPTODMA_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8838}]
set  CM_PER_L3_INSTR_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8840}]
set  CM_PER_MSTR_EXPS_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8848}]
set  CM_PER_OCMCRAM_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8850}]
set  CM_PER_SHA0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8858}]
set  CM_PER_SLV_EXPS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8860}]
set  CM_PER_VPFE0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8868}]
set  CM_PER_VPFE1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8870}]
set  CM_PER_TPCC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8878}]
set  CM_PER_TPTC0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8880}]
set  CM_PER_TPTC1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8888}]
set  CM_PER_TPTC2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8890}]
set  CM_PER_DLL_AGING_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8898}]
set  CM_PER_L4HS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a0}]
set  CM_PER_L4FW_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a8}]
set  CM_PER_L3S_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8a00}]
set  CM_PER_GPMC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a20}]
set  CM_PER_IEEE5000_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8a28}]
set  CM_PER_MCASP0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a38}]
set  CM_PER_MCASP1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a40}]
set  CM_PER_MMC2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a48}]
set  CM_PER_QSPI_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a58}]
set  CM_PER_USB_OTG_SS0_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a60}]
set  CM_PER_USB_OTG_SS1_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a68}]
set  CM_PER_ICSS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8b00}]
set  CM_PER_ICSS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8b20}]
set  CM_PER_L4LS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8c00}]
set  CM_PER_L4LS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8c20}]
set  CM_PER_DCAN0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c28}]
set  CM_PER_DCAN1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c30}]
set  CM_PER_EPWMSS0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c38}]
set  CM_PER_EPWMSS1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c40}]
set  CM_PER_EPWMSS2_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c48}]
set  CM_PER_EPWMSS3_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c50}]
set  CM_PER_EPWMSS4_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c58}]
set  CM_PER_EPWMSS5_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c60}]
set  CM_PER_ELM_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8c68}]
set  CM_PER_GPIO1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c78}]
set  CM_PER_GPIO2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c80}]
set  CM_PER_GPIO3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c88}]
set  CM_PER_GPIO4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c90}]
set  CM_PER_GPIO5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c98}]
set  CM_PER_HDQ1W_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8ca0}]
set  CM_PER_I2C1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8ca8}]
set  CM_PER_I2C2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cb0}]
set  CM_PER_MAILBOX0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8cb8}]
set  CM_PER_MMC0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc0}]
set  CM_PER_MMC1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc8}]
set  CM_PER_PKA_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8cd0}]
set  CM_PER_RNG_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8ce0}]
set  CM_PER_SPARE0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8ce8}]
set  CM_PER_SPARE1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8cf0}]
set  CM_PER_SPI0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d00}]
set  CM_PER_SPI1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d08}]
set  CM_PER_SPI2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d10}]
set  CM_PER_SPI3_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d18}]
set  CM_PER_SPI4_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d20}]
set  CM_PER_SPINLOCK_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8d28}]
set  CM_PER_TIMER2_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d30}]
set  CM_PER_TIMER3_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d38}]
set  CM_PER_TIMER4_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d40}]
set  CM_PER_TIMER5_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d48}]
set  CM_PER_TIMER6_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d50}]
set  CM_PER_TIMER7_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d58}]
set  CM_PER_TIMER8_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d60}]
set  CM_PER_TIMER9_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d68}]
set  CM_PER_TIMER10_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d70}]
set  CM_PER_TIMER11_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d78}]
set  CM_PER_UART1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d80}]
set  CM_PER_UART2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d88}]
set  CM_PER_UART3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d90}]
set  CM_PER_UART4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d98}]
set  CM_PER_UART5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8da0}]
set  CM_PER_USBPHYOCP2SCP0_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8db8}]
set  CM_PER_USBPHYOCP2SCP1_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8dc0}]
set  CM_PER_EMIF_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8f00}]
set  CM_PER_EMIF_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8f20}]
set  CM_PER_DLL_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8f28}]
set  CM_PER_EMIF_FW_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8f30}]
set  CM_PER_OTFA_EMIF_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8f38}]
set  CM_PER_DSS_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9200}]
set  CM_PER_DSS_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x9220}]
set  CM_PER_CPSW_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x9300}]
set  CM_PER_CPGMAC0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x9320}]
set  CM_PER_OCPWP_L3_CLKSTCTRL       [expr       {$PRCM_BASE_ADDR     +  0x9400}]
set  CM_PER_OCPWP_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9420}]

set  CONTROL_BASE_ADDR               0x44e10000
set  CONTROL_STATUS                  [expr       {$CONTROL_BASE_ADDR  +  0x0040}]
set  DEVICE_ID                       [expr       {$CONTROL_BASE_ADDR  +  0x0600}]
set  DEV_FEATURE                     [expr       {$CONTROL_BASE_ADDR  +  0x0604}]
set  DEV_ATTRIBUTE                   [expr       {$CONTROL_BASE_ADDR  +  0x0610}]
set  MAC_ID0_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0630}]
set  MAC_ID0_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x0634}]
set  MAC_ID1_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0638}]
set  MAC_ID1_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x063c}]
set  USB_VID_PID                     [expr       {$CONTROL_BASE_ADDR  +  0x07f4}]
set  CONTROL_CONF_ECAP0_IN_PWM0_OUT  [expr       {$CONTROL_BASE_ADDR  +  0x0964}]
set  CONTROL_CONF_SPI4_CS0           [expr       {$CONTROL_BASE_ADDR  +  0x0a5c}]
set  CONTROL_CONF_SPI2_SCLK          [expr       {$CONTROL_BASE_ADDR  +  0x0a60}]
set  CONTROL_CONF_SPI2_D0            [expr       {$CONTROL_BASE_ADDR  +  0x0a64}]
set  CONTROL_CONF_XDMA_EVENT_INTR0   [expr       {$CONTROL_BASE_ADDR  +  0x0a70}]
set  CONTROL_CONF_XDMA_EVENT_INTR1   [expr       {$CONTROL_BASE_ADDR  +  0x0a74}]
set  CONTROL_CONF_GPMC_A0            [expr       {$CONTROL_BASE_ADDR  +  0x0840}]
set  DDR_IO_CTRL                     [expr       {$CONTROL_BASE_ADDR  +  0x0e04}]
set  VTP_CTRL_REG                    [expr       {$CONTROL_BASE_ADDR  +  0x0e0c}]
set  VREF_CTRL                       [expr       {$CONTROL_BASE_ADDR  +  0x0e14}]
set  DDR_CKE_CTRL                    [expr       {$CONTROL_BASE_ADDR  +  0x131c}]
set  DDR_ADDRCTRL_IOCTRL             [expr       {$CONTROL_BASE_ADDR  +  0x1404}]
set  DDR_ADDRCTRL_WD0_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x1408}]
set  DDR_ADDRCTRL_WD1_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x140c}]
set  DDR_DATA0_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1440}]
set  DDR_DATA1_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1444}]
set  DDR_DATA2_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1448}]
set  DDR_DATA3_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x144c}]
set  EMIF_SDRAM_CONFIG_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1460}]
set  EMIF_SDRAM_STATUS_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1464}]

set  GPIO0_BASE_ADDR                 0x44e07000
set  GPIO0_SYSCONFIG                 [expr       {$GPIO0_BASE_ADDR    +  0x0010}]
set  GPIO0_SYSSTATUS                 [expr       {$GPIO0_BASE_ADDR    +  0x0114}]
set  GPIO0_CTRL                      [expr       {$GPIO0_BASE_ADDR    +  0x0130}]
set  GPIO0_OE                        [expr       {$GPIO0_BASE_ADDR    +  0x0134}]
set  GPIO0_CLEARDATAOUT              [expr       {$GPIO0_BASE_ADDR    +  0x0190}]
set  GPIO0_SETDATAOUT                [expr       {$GPIO0_BASE_ADDR    +  0x0194}]

set  GPIO5_BASE_ADDR                 0x48322000
set  GPIO5_SYSCONFIG                 [expr       {$GPIO5_BASE_ADDR    +  0x0010}]
set  GPIO5_SYSSTATUS                 [expr       {$GPIO5_BASE_ADDR    +  0x0114}]
set  GPIO5_CTRL                      [expr       {$GPIO5_BASE_ADDR    +  0x0130}]
set  GPIO5_OE                        [expr       {$GPIO5_BASE_ADDR    +  0x0134}]
set  GPIO5_CLEARDATAOUT              [expr       {$GPIO5_BASE_ADDR    +  0x0190}]
set  GPIO5_SETDATAOUT                [expr       {$GPIO5_BASE_ADDR    +  0x0194}]

set  GPIO1_BASE_ADDR                 0x4804c000
set  GPIO1_SYSCONFIG                 [expr       {$GPIO1_BASE_ADDR    +  0x0010}]
set  GPIO1_SYSSTATUS                 [expr       {$GPIO1_BASE_ADDR    +  0x0114}]
set  GPIO1_CTRL                      [expr       {$GPIO1_BASE_ADDR    +  0x0130}]
set  GPIO1_OE                        [expr       {$GPIO1_BASE_ADDR    +  0x0134}]
set  GPIO1_CLEARDATAOUT              [expr       {$GPIO1_BASE_ADDR    +  0x0190}]
set  GPIO1_SETDATAOUT                [expr       {$GPIO1_BASE_ADDR    +  0x0194}]

set  EMIF_BASE_ADDR                  0x4c000000
set  EMIF_STATUS                     [expr       {$EMIF_BASE_ADDR     +  0x0004}]
set  EMIF_SDRAM_CONFIG               [expr       {$EMIF_BASE_ADDR     +  0x0008}]
set  EMIF_SDRAM_CONFIG_2             [expr       {$EMIF_BASE_ADDR     +  0x000c}]
set  EMIF_SDRAM_REF_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0010}]
set  EMIF_SDRAM_REF_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0014}]
set  EMIF_SDRAM_TIM_1                [expr       {$EMIF_BASE_ADDR     +  0x0018}]
set  EMIF_SDRAM_TIM_1_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x001c}]
set  EMIF_SDRAM_TIM_2                [expr       {$EMIF_BASE_ADDR     +  0x0020}]
set  EMIF_SDRAM_TIM_2_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x0024}]
set  EMIF_SDRAM_TIM_3                [expr       {$EMIF_BASE_ADDR     +  0x0028}]
set  EMIF_SDRAM_TIM_3_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x002c}]
set  EMIF_LPDDR2_NVM_TIM             [expr       {$EMIF_BASE_ADDR     +  0x0030}]
set  EMIF_LPDDR2_NVM_TIM_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0034}]
set  EMIF_PWR_MGMT_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x0038}]
set  EMIF_PWR_MGMT_CTRL_SHDW         [expr       {$EMIF_BASE_ADDR     +  0x003c}]
set  EMIF_LPDDR2_MODE_REG_DATA       [expr       {$EMIF_BASE_ADDR     +  0x0040}]
set  EMIF_LPDDR2_MODE_REG_CFG        [expr       {$EMIF_BASE_ADDR     +  0x0050}]
set  EMIF_OCP_CONFIG                 [expr       {$EMIF_BASE_ADDR     +  0x0054}]
set  EMIF_OCP_CFG_VAL_1              [expr       {$EMIF_BASE_ADDR     +  0x0058}]
set  EMIF_OCP_CFG_VAL_2              [expr       {$EMIF_BASE_ADDR     +  0x005c}]
set  EMIF_IODFT_TLGC                 [expr       {$EMIF_BASE_ADDR     +  0x0060}]
set  EMIF_IODFT_CTRL_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0064}]
set  EMIF_IODFT_ADDR_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0068}]
set  EMIF_IODFT_DATA_MISR_RSLT_1     [expr       {$EMIF_BASE_ADDR     +  0x006c}]
set  EMIF_IODFT_DATA_MISR_RSLT_2     [expr       {$EMIF_BASE_ADDR     +  0x0070}]
set  EMIF_IODFT_DATA_MISR_RSLT_3     [expr       {$EMIF_BASE_ADDR     +  0x0074}]
set  EMIF_PERF_CNT_1                 [expr       {$EMIF_BASE_ADDR     +  0x0080}]
set  EMIF_PERF_CNT_2                 [expr       {$EMIF_BASE_ADDR     +  0x0084}]
set  EMIF_PERF_CNT_CFG               [expr       {$EMIF_BASE_ADDR     +  0x0088}]
set  EMIF_PERF_CNT_SEL               [expr       {$EMIF_BASE_ADDR     +  0x008c}]
set  EMIF_PERF_CNT_TIM               [expr       {$EMIF_BASE_ADDR     +  0x0090}]
set  EMIF_MISC_REG                   [expr       {$EMIF_BASE_ADDR     +  0x0094}]
set  EMIF_DLL_CALIB_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0098}]
set  EMIF_DLL_CALIB_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x009c}]
set  EMIF_IRQ_EOI                    [expr       {$EMIF_BASE_ADDR     +  0x00a0}]
set  EMIF_IRQSTATUS_RAW_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00a4}]
set  EMIF_IRQSTATUS_SYS              [expr       {$EMIF_BASE_ADDR     +  0x00ac}]
set  EMIF_IRQENABLE_SET_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00b4}]
set  EMIF_IRQENABLE_CLR_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00bc}]
set  EMIF_ZQ_CONFIG                  [expr       {$EMIF_BASE_ADDR     +  0x00c8}]
set  EMIF_TEMP_ALERT_CONFIG          [expr       {$EMIF_BASE_ADDR     +  0x00cc}]
set  EMIF_OCP_ERR_LOG                [expr       {$EMIF_BASE_ADDR     +  0x00d0}]
set  EMIF_RDWR_LVL_RMP_WIN           [expr       {$EMIF_BASE_ADDR     +  0x00d4}]
set  EMIF_RDWR_LVL_RMP_CTRL          [expr       {$EMIF_BASE_ADDR     +  0x00d8}]
set  EMIF_RDWR_LVL_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x00dc}]
set  EMIF_DDR_PHY_CTRL_1             [expr       {$EMIF_BASE_ADDR     +  0x00e4}]
set  EMIF_DDR_PHY_CTRL_1_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x00e8}]
set  EMIF_DDR_PHY_CTRL_2             [expr       {$EMIF_BASE_ADDR     +  0x00ec}]
set  EMIF_PRI_COS_MAP                [expr       {$EMIF_BASE_ADDR     +  0x0100}]
set  EMIF_CONNID_COS_1_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0104}]
set  EMIF_CONNID_COS_2_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0108}]
set  ECC_CTRL                        [expr       {$EMIF_BASE_ADDR     +  0x0110}]
set  ECC_ADDR_RNG_1                  [expr       {$EMIF_BASE_ADDR     +  0x0114}]
set  ECC_ADDR_RNG_2                  [expr       {$EMIF_BASE_ADDR     +  0x0118}]
set  EMIF_RD_WR_EXEC_THRSH           [expr       {$EMIF_BASE_ADDR     +  0x0120}]
set  COS_CONFIG                      [expr       {$EMIF_BASE_ADDR     +  0x0124}]

set  PHY_STATUS_1                    [expr       {$EMIF_BASE_ADDR     +  0x0144}]
set  PHY_STATUS_2                    [expr       {$EMIF_BASE_ADDR     +  0x0148}]
set  PHY_STATUS_3                    [expr       {$EMIF_BASE_ADDR     +  0x014c}]
set  PHY_STATUS_4                    [expr       {$EMIF_BASE_ADDR     +  0x0150}]
set  PHY_STATUS_5                    [expr       {$EMIF_BASE_ADDR     +  0x0154}]
set  PHY_STATUS_6                    [expr       {$EMIF_BASE_ADDR     +  0x0158}]
set  PHY_STATUS_7                    [expr       {$EMIF_BASE_ADDR     +  0x015c}]
set  PHY_STATUS_8                    [expr       {$EMIF_BASE_ADDR     +  0x0160}]
set  PHY_STATUS_9                    [expr       {$EMIF_BASE_ADDR     +  0x0164}]
set  PHY_STATUS_10                   [expr       {$EMIF_BASE_ADDR     +  0x0168}]
set  PHY_STATUS_11                   [expr       {$EMIF_BASE_ADDR     +  0x016c}]
set  PHY_STATUS_12                   [expr       {$EMIF_BASE_ADDR     +  0x0170}]
set  PHY_STATUS_13                   [expr       {$EMIF_BASE_ADDR     +  0x0174}]
set  PHY_STATUS_14                   [expr       {$EMIF_BASE_ADDR     +  0x0178}]
set  PHY_STATUS_15                   [expr       {$EMIF_BASE_ADDR     +  0x017c}]
set  PHY_STATUS_16                   [expr       {$EMIF_BASE_ADDR     +  0x0180}]
set  PHY_STATUS_17                   [expr       {$EMIF_BASE_ADDR     +  0x0184}]
set  PHY_STATUS_18                   [expr       {$EMIF_BASE_ADDR     +  0x0188}]
set  PHY_STATUS_19                   [expr       {$EMIF_BASE_ADDR     +  0x018c}]
set  PHY_STATUS_20                   [expr       {$EMIF_BASE_ADDR     +  0x0190}]
set  PHY_STATUS_21                   [expr       {$EMIF_BASE_ADDR     +  0x0194}]
set  PHY_STATUS_22                   [expr       {$EMIF_BASE_ADDR     +  0x0198}]
set  PHY_STATUS_23                   [expr       {$EMIF_BASE_ADDR     +  0x019c}]
set  PHY_STATUS_24                   [expr       {$EMIF_BASE_ADDR     +  0x01a0}]
set  PHY_STATUS_25                   [expr       {$EMIF_BASE_ADDR     +  0x01a4}]
set  PHY_STATUS_26                   [expr       {$EMIF_BASE_ADDR     +  0x01a8}]
set  PHY_STATUS_27                   [expr       {$EMIF_BASE_ADDR     +  0x01ac}]
set  PHY_STATUS_28                   [expr       {$EMIF_BASE_ADDR     +  0x01b0}]

set  EXT_PHY_CTRL_1                  [expr       {$EMIF_BASE_ADDR     +  0x0200}]
set  EXT_PHY_CTRL_1_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0204}]
set  EXT_PHY_CTRL_2                  [expr       {$EMIF_BASE_ADDR     +  0x0208}]
set  EXT_PHY_CTRL_2_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x020c}]
set  EXT_PHY_CTRL_3                  [expr       {$EMIF_BASE_ADDR     +  0x0210}]
set  EXT_PHY_CTRL_3_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0214}]
set  EXT_PHY_CTRL_4                  [expr       {$EMIF_BASE_ADDR     +  0x0218}]
set  EXT_PHY_CTRL_4_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x021c}]
set  EXT_PHY_CTRL_5                  [expr       {$EMIF_BASE_ADDR     +  0x0220}]
set  EXT_PHY_CTRL_5_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0224}]
set  EXT_PHY_CTRL_6                  [expr       {$EMIF_BASE_ADDR     +  0x0228}]
set  EXT_PHY_CTRL_6_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x022c}]
set  EXT_PHY_CTRL_7                  [expr       {$EMIF_BASE_ADDR     +  0x0230}]
set  EXT_PHY_CTRL_7_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0234}]
set  EXT_PHY_CTRL_8                  [expr       {$EMIF_BASE_ADDR     +  0x0238}]
set  EXT_PHY_CTRL_8_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x023c}]
set  EXT_PHY_CTRL_9                  [expr       {$EMIF_BASE_ADDR     +  0x0240}]
set  EXT_PHY_CTRL_9_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0244}]
set  EXT_PHY_CTRL_10                 [expr       {$EMIF_BASE_ADDR     +  0x0248}]
set  EXT_PHY_CTRL_10_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x024c}]
set  EXT_PHY_CTRL_11                 [expr       {$EMIF_BASE_ADDR     +  0x0250}]
set  EXT_PHY_CTRL_11_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0254}]
set  EXT_PHY_CTRL_12                 [expr       {$EMIF_BASE_ADDR     +  0x0258}]
set  EXT_PHY_CTRL_12_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x025c}]
set  EXT_PHY_CTRL_13                 [expr       {$EMIF_BASE_ADDR     +  0x0260}]
set  EXT_PHY_CTRL_13_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0264}]
set  EXT_PHY_CTRL_14                 [expr       {$EMIF_BASE_ADDR     +  0x0268}]
set  EXT_PHY_CTRL_14_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x026c}]
set  EXT_PHY_CTRL_15                 [expr       {$EMIF_BASE_ADDR     +  0x0270}]
set  EXT_PHY_CTRL_15_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0274}]
set  EXT_PHY_CTRL_16                 [expr       {$EMIF_BASE_ADDR     +  0x0278}]
set  EXT_PHY_CTRL_16_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x027c}]
set  EXT_PHY_CTRL_17                 [expr       {$EMIF_BASE_ADDR     +  0x0280}]
set  EXT_PHY_CTRL_17_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0284}]
set  EXT_PHY_CTRL_18                 [expr       {$EMIF_BASE_ADDR     +  0x0288}]
set  EXT_PHY_CTRL_18_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x028c}]
set  EXT_PHY_CTRL_19                 [expr       {$EMIF_BASE_ADDR     +  0x0290}]
set  EXT_PHY_CTRL_19_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0294}]
set  EXT_PHY_CTRL_20                 [expr       {$EMIF_BASE_ADDR     +  0x0298}]
set  EXT_PHY_CTRL_20_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x029c}]
set  EXT_PHY_CTRL_21                 [expr       {$EMIF_BASE_ADDR     +  0x02a0}]
set  EXT_PHY_CTRL_21_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02a4}]
set  EXT_PHY_CTRL_22                 [expr       {$EMIF_BASE_ADDR     +  0x02a8}]
set  EXT_PHY_CTRL_22_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ac}]
set  EXT_PHY_CTRL_23                 [expr       {$EMIF_BASE_ADDR     +  0x02b0}]
set  EXT_PHY_CTRL_23_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02b4}]
set  EXT_PHY_CTRL_24                 [expr       {$EMIF_BASE_ADDR     +  0x02b8}]
set  EXT_PHY_CTRL_24_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02bc}]
set  EXT_PHY_CTRL_25                 [expr       {$EMIF_BASE_ADDR     +  0x02c0}]
set  EXT_PHY_CTRL_25_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02c4}]
set  EXT_PHY_CTRL_26                 [expr       {$EMIF_BASE_ADDR     +  0x02c8}]
set  EXT_PHY_CTRL_26_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02cc}]
set  EXT_PHY_CTRL_27                 [expr       {$EMIF_BASE_ADDR     +  0x02d0}]
set  EXT_PHY_CTRL_27_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02d4}]
set  EXT_PHY_CTRL_28                 [expr       {$EMIF_BASE_ADDR     +  0x02d8}]
set  EXT_PHY_CTRL_28_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02dc}]
set  EXT_PHY_CTRL_29                 [expr       {$EMIF_BASE_ADDR     +  0x02e0}]
set  EXT_PHY_CTRL_29_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02e4}]
set  EXT_PHY_CTRL_30                 [expr       {$EMIF_BASE_ADDR     +  0x02e8}]
set  EXT_PHY_CTRL_30_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ec}]
set  EXT_PHY_CTRL_31                 [expr       {$EMIF_BASE_ADDR     +  0x02f0}]
set  EXT_PHY_CTRL_31_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02f4}]
set  EXT_PHY_CTRL_32                 [expr       {$EMIF_BASE_ADDR     +  0x02f8}]
set  EXT_PHY_CTRL_32_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02fc}]
set  EXT_PHY_CTRL_33                 [expr       {$EMIF_BASE_ADDR     +  0x0300}]
set  EXT_PHY_CTRL_33_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0304}]
set  EXT_PHY_CTRL_34                 [expr       {$EMIF_BASE_ADDR     +  0x0308}]
set  EXT_PHY_CTRL_34_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x030c}]
set  EXT_PHY_CTRL_35                 [expr       {$EMIF_BASE_ADDR     +  0x0310}]
set  EXT_PHY_CTRL_35_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0314}]
set  EXT_PHY_CTRL_36                 [expr       {$EMIF_BASE_ADDR     +  0x0318}]
set  EXT_PHY_CTRL_36_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x031c}]

set  WDT1_BASE_ADDR                  0x44e35000
set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]

set  RTC_BASE_ADDR                   0x44e3e000
set  RTC_KICK0R                      [expr       {$RTC_BASE_ADDR      +  0x6c}]
set  RTC_KICK1R                      [expr       {$RTC_BASE_ADDR      +  0x70}]


if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME am437x
}

set JRC_MODULE		icepick_d
set DEBUGSS_MODULE	debugss
set M3_MODULE		m3_wakeupss

set JRC_NAME		$_CHIPNAME.$JRC_MODULE
set DEBUGSS_NAME	$_CHIPNAME.$DEBUGSS_MODULE
set M3_NAME		$_CHIPNAME.$M3_MODULE
set _TARGETNAME		$_CHIPNAME.mpuss

#
# M3 WakeupSS DAP
#
if { [info exists M3_DAP_TAPID] } {
	set _M3_DAP_TAPID $M3_DAP_TAPID
} else {
	set _M3_DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
dap create $M3_NAME.dap -chain-position $M3_NAME

#
# DebugSS DAP
#
if { [info exists DAP_TAPID] } {
   set _DAP_TAPID $DAP_TAPID
} else {
   set _DAP_TAPID 0x46b6902f
}
jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME

#
# ICEpick-D (JTAG route controller)
#
if { [info exists JRC_TAPID] } {
   set _JRC_TAPID $JRC_TAPID
} else {
   set _JRC_TAPID 0x0b98c02f
}
jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
 # some TCK tycles are required to activate the DEBUG power domain
jtag configure $JRC_NAME -event post-reset "runtest 100"

#
# Cortex-A9 target
#
target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000


# SRAM: 256K at 0x4030.0000
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000

# Disables watchdog timer after reset otherwise board won't stay in
# halted state.
proc disable_watchdog { } {
	global WDT1_WSPR
	global WDT1_W_PEND_WSPR
	global _TARGETNAME

	set curstate [$_TARGETNAME curstate]

	if { [string compare $curstate halted] == 0 } {
		set WDT_DISABLE_SEQ1	0xaaaa
		set WDT_DISABLE_SEQ2	0x5555

		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1

		# Empty body to make sure this executes as fast as possible.
		# We don't want any delays here otherwise romcode might start
		# executing and end up changing state of certain IPs.
		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }

		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
		while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
	}
}

proc ceil { x y } {
	return [ expr {($x + $y - 1) / $y} ]
}

proc device_type { } {
	global CONTROL_STATUS

	set tmp [ mrw $CONTROL_STATUS ]
	set tmp [ expr {$tmp & 0x700} ]
	set tmp [ expr {$tmp >> 8} ]

	return $tmp
}

proc get_input_clock_frequency { } {
	global CONTROL_STATUS

	if { [ device_type ] != 3 } {
		error "Unknown device type\n"
		return -1
	}

	set freq [ mrw $CONTROL_STATUS ]
	set freq [ expr {$freq & 0x00c00000} ]
	set freq [ expr {$freq >> 22} ]

	switch $freq {
		0 {
			set CLKIN 19200000
		}

		1 {
			set CLKIN 24000000
		}

		2 {
			set CLKIN 25000000
		}

		3 {
			set CLKIN 26000000
		}
	}

	return $CLKIN
}

proc mpu_pll_config { CLKIN N M M2 } {
	global CM_CLKMODE_DPLL_MPU
	global CM_CLKSEL_DPLL_MPU
	global CM_DIV_M2_DPLL_MPU
	global CM_IDLEST_DPLL_MPU

	set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
	set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]

	mww $CM_CLKMODE_DPLL_MPU 0x4
	while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }

	set clksel [ expr {$clksel & (~0x7ffff)} ]
	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
	mww $CM_CLKSEL_DPLL_MPU $clksel

	set div_m2 [ expr {$div_m2 & (~0x1f)} ]
	set div_m2 [ expr {$div_m2 | $M2} ]
	mww $CM_DIV_M2_DPLL_MPU $div_m2

	mww $CM_CLKMODE_DPLL_MPU 0x7
	while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }

	echo "MPU DPLL locked"
}

proc core_pll_config { CLKIN N M M4 M5 M6 } {
	global CM_CLKMODE_DPLL_CORE
	global CM_CLKSEL_DPLL_CORE
	global CM_DIV_M4_DPLL_CORE
	global CM_DIV_M5_DPLL_CORE
	global CM_DIV_M6_DPLL_CORE
	global CM_IDLEST_DPLL_CORE

	set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]

	mww $CM_CLKMODE_DPLL_CORE 0x4
	while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }

	set clksel [ expr {$clksel & (~0x7ffff)} ]
	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
	mww $CM_CLKSEL_DPLL_CORE $clksel
	mww $CM_DIV_M4_DPLL_CORE $M4
	mww $CM_DIV_M5_DPLL_CORE $M5
	mww $CM_DIV_M6_DPLL_CORE $M6

	mww $CM_CLKMODE_DPLL_CORE 0x7
	while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }

	echo "CORE DPLL locked"
}

proc per_pll_config { CLKIN N M M2 } {
	global CM_CLKMODE_DPLL_PER
	global CM_CLKSEL_DPLL_PER
	global CM_DIV_M2_DPLL_PER
	global CM_IDLEST_DPLL_PER

	set x [ expr {$M * $CLKIN / 1000000} ]
	set y [ expr {($N + 1) * 250} ]
	set sd [ ceil $x $y ]

	set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
	set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]

	mww $CM_CLKMODE_DPLL_PER 0x4
	while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }

	set clksel [ expr {$clksel & (~0xff0fffff)} ]
	set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
	set clksel [ expr {$clksel | ($sd << 24)} ]
	mww $CM_CLKSEL_DPLL_PER $clksel

	set div_m2 [ expr {0xffffff80 | $M2} ]

	mww $CM_CLKMODE_DPLL_PER 0x7
	while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }

	echo "PER DPLL locked"
}

proc ddr_pll_config { CLKIN N M M2 M4 } {
	global CM_CLKMODE_DPLL_DDR
	global CM_CLKSEL_DPLL_DDR
	global CM_DIV_M2_DPLL_DDR
	global CM_DIV_M4_DPLL_DDR
	global CM_IDLEST_DPLL_DDR

	set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
	set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]

	mww $CM_CLKMODE_DPLL_DDR 0x4
	while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }

	set clksel [ expr {$clksel & (~0x7ffff)} ]
	set clksel [ expr {$clksel | ($M << 8) | $N} ]
	mww $CM_CLKSEL_DPLL_DDR $clksel

	set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ]
	mww $CM_DIV_M2_DPLL_DDR $div_m2
	mww $CM_DIV_M4_DPLL_DDR $M4

	mww $CM_CLKMODE_DPLL_DDR 0x7
	while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }

	echo "DDR DPLL Locked"
}

proc config_opp100 { } {
	set CLKIN [ get_input_clock_frequency ]

	if { $CLKIN == -1 } {
		return -1
	}

	switch $CLKIN {
		24000000 {
			mpu_pll_config   $CLKIN  0  25   1
			core_pll_config  $CLKIN  2  125  10  8  4
			per_pll_config   $CLKIN  9  400  5
			ddr_pll_config   $CLKIN  2  50   1   2
		}

		25000000 {
			mpu_pll_config   $CLKIN  0  24   1
			core_pll_config  $CLKIN  0  40   10  8  4
			per_pll_config   $CLKIN  9  384  5
			ddr_pll_config   $CLKIN  0  16   1   2
		}

		26000000 {
			mpu_pll_config   $CLKIN  12  300  1
			core_pll_config  $CLKIN  12  500  10  8  4
			per_pll_config   $CLKIN  12  480  5
			ddr_pll_config   $CLKIN  12  200  1   2
		}

		19200000 {
			mpu_pll_config   $CLKIN  3   125  1
			core_pll_config  $CLKIN  11  625  10  8  4
			per_pll_config   $CLKIN  7   400  5
			ddr_pll_config   $CLKIN  2   125  1   2
		}
	}
}

proc emif_prcm_clk_enable { } {
	global CM_PER_EMIF_FW_CLKCTRL
	global CM_PER_EMIF_CLKCTRL

	mww $CM_PER_EMIF_FW_CLKCTRL 0x02
	mww $CM_PER_EMIF_CLKCTRL 0x02

	while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
}

proc vtp_enable { } {
	global VTP_CTRL_REG

	set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
	mww $VTP_CTRL_REG $vtp

	set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
	mww $VTP_CTRL_REG $vtp

	set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
	mww $VTP_CTRL_REG $vtp

}

proc config_ddr_ioctrl { } {
	global DDR_ADDRCTRL_IOCTRL
	global DDR_ADDRCTRL_WD0_IOCTRL
	global DDR_ADDRCTRL_WD1_IOCTRL
	global DDR_CKE_CTRL
	global DDR_DATA0_IOCTRL
	global DDR_DATA1_IOCTRL
	global DDR_DATA2_IOCTRL
	global DDR_DATA3_IOCTRL
	global DDR_IO_CTRL

	mww $DDR_ADDRCTRL_IOCTRL	0x84
	mww $DDR_ADDRCTRL_WD0_IOCTRL	0x00
	mww $DDR_ADDRCTRL_WD1_IOCTRL	0x00
	mww $DDR_DATA0_IOCTRL		0x84
	mww $DDR_DATA1_IOCTRL		0x84
	mww $DDR_DATA2_IOCTRL		0x84
	mww $DDR_DATA3_IOCTRL		0x84

	mww $DDR_IO_CTRL		0x00
	mww $DDR_CKE_CTRL		0x03
}

proc config_ddr_phy { } {
	global EMIF_DDR_PHY_CTRL_1
	global EMIF_DDR_PHY_CTRL_1_SHDW

	global EXT_PHY_CTRL_1
	global EXT_PHY_CTRL_1_SHDW
	global EXT_PHY_CTRL_2
	global EXT_PHY_CTRL_2_SHDW
	global EXT_PHY_CTRL_3
	global EXT_PHY_CTRL_3_SHDW
	global EXT_PHY_CTRL_4
	global EXT_PHY_CTRL_4_SHDW
	global EXT_PHY_CTRL_5
	global EXT_PHY_CTRL_5_SHDW
	global EXT_PHY_CTRL_6
	global EXT_PHY_CTRL_6_SHDW
	global EXT_PHY_CTRL_7
	global EXT_PHY_CTRL_7_SHDW
	global EXT_PHY_CTRL_8
	global EXT_PHY_CTRL_8_SHDW
	global EXT_PHY_CTRL_9
	global EXT_PHY_CTRL_9_SHDW
	global EXT_PHY_CTRL_10
	global EXT_PHY_CTRL_10_SHDW
	global EXT_PHY_CTRL_11
	global EXT_PHY_CTRL_11_SHDW
	global EXT_PHY_CTRL_12
	global EXT_PHY_CTRL_12_SHDW
	global EXT_PHY_CTRL_13
	global EXT_PHY_CTRL_13_SHDW
	global EXT_PHY_CTRL_14
	global EXT_PHY_CTRL_14_SHDW
	global EXT_PHY_CTRL_15
	global EXT_PHY_CTRL_15_SHDW
	global EXT_PHY_CTRL_16
	global EXT_PHY_CTRL_16_SHDW
	global EXT_PHY_CTRL_17
	global EXT_PHY_CTRL_17_SHDW
	global EXT_PHY_CTRL_18
	global EXT_PHY_CTRL_18_SHDW
	global EXT_PHY_CTRL_19
	global EXT_PHY_CTRL_19_SHDW
	global EXT_PHY_CTRL_20
	global EXT_PHY_CTRL_20_SHDW
	global EXT_PHY_CTRL_21
	global EXT_PHY_CTRL_21_SHDW
	global EXT_PHY_CTRL_22
	global EXT_PHY_CTRL_22_SHDW
	global EXT_PHY_CTRL_23
	global EXT_PHY_CTRL_23_SHDW
	global EXT_PHY_CTRL_24
	global EXT_PHY_CTRL_24_SHDW
	global EXT_PHY_CTRL_25
	global EXT_PHY_CTRL_25_SHDW
	global EXT_PHY_CTRL_26
	global EXT_PHY_CTRL_26_SHDW
	global EXT_PHY_CTRL_27
	global EXT_PHY_CTRL_27_SHDW
	global EXT_PHY_CTRL_28
	global EXT_PHY_CTRL_28_SHDW
	global EXT_PHY_CTRL_29
	global EXT_PHY_CTRL_29_SHDW
	global EXT_PHY_CTRL_30
	global EXT_PHY_CTRL_30_SHDW
	global EXT_PHY_CTRL_31
	global EXT_PHY_CTRL_31_SHDW
	global EXT_PHY_CTRL_32
	global EXT_PHY_CTRL_32_SHDW
	global EXT_PHY_CTRL_33
	global EXT_PHY_CTRL_33_SHDW
	global EXT_PHY_CTRL_34
	global EXT_PHY_CTRL_34_SHDW
	global EXT_PHY_CTRL_35
	global EXT_PHY_CTRL_35_SHDW
	global EXT_PHY_CTRL_36
	global EXT_PHY_CTRL_36_SHDW

	mww $EMIF_DDR_PHY_CTRL_1	0x8009
	mww $EMIF_DDR_PHY_CTRL_1_SHDW	0x8009

	set slave_ratio		0x80
	set gatelvl_init_ratio	0x20
	set wr_dqs_slave_delay	0x60
	set rd_dqs_slave_delay	0x60
	set dq_offset		0x40
	set gatelvl_init_mode	0x01
	set wr_data_slave_delay	0x80
	set gatelvl_num_dq0 0x0f
	set wrlvl_num_dq0 0x0f

	mww $EXT_PHY_CTRL_1        [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
	mww $EXT_PHY_CTRL_1_SHDW   [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
	mww $EXT_PHY_CTRL_26       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_26_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_27       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_27_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_28       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_28_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_29       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_29_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_30       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_30_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
	mww $EXT_PHY_CTRL_31       0x00
	mww $EXT_PHY_CTRL_31_SHDW  0x00
	mww $EXT_PHY_CTRL_32       0x00
	mww $EXT_PHY_CTRL_32_SHDW  0x00
	mww $EXT_PHY_CTRL_33       0x00
	mww $EXT_PHY_CTRL_33_SHDW  0x00
	mww $EXT_PHY_CTRL_34       0x00
	mww $EXT_PHY_CTRL_34_SHDW  0x00
	mww $EXT_PHY_CTRL_35       0x00
	mww $EXT_PHY_CTRL_35_SHDW  0x00
	mww $EXT_PHY_CTRL_22       0x00
	mww $EXT_PHY_CTRL_22_SHDW  0x00
	mww $EXT_PHY_CTRL_23       [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
	mww $EXT_PHY_CTRL_23_SHDW  [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
	mww $EXT_PHY_CTRL_24       [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ]
	mww $EXT_PHY_CTRL_24_SHDW  [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ]
	mww $EXT_PHY_CTRL_25       [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
	mww $EXT_PHY_CTRL_25_SHDW  [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
	mww $EXT_PHY_CTRL_36       [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
	mww $EXT_PHY_CTRL_36_SHDW  [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
}

proc config_ddr_timing { } {
	global EMIF_SDRAM_TIM_1
	global EMIF_SDRAM_TIM_2
	global EMIF_SDRAM_TIM_3
	global EMIF_SDRAM_TIM_1_SHDW
	global EMIF_SDRAM_TIM_2_SHDW
	global EMIF_SDRAM_TIM_3_SHDW
	global EMIF_ZQ_CONFIG

	mww $EMIF_SDRAM_TIM_1		0xeaaad4db
	mww $EMIF_SDRAM_TIM_1_SHDW	0xeaaad4db

	mww $EMIF_SDRAM_TIM_2		0x266b7fda
	mww $EMIF_SDRAM_TIM_2_SHDW	0x266b7fda

	mww $EMIF_SDRAM_TIM_3		0x107f8678
	mww $EMIF_SDRAM_TIM_3_SHDW	0x107f8678

	mww $EMIF_ZQ_CONFIG		0x50074be4
}

proc config_ddr_pm { } {
	global EMIF_PWR_MGMT_CTRL
	global EMIF_PWR_MGMT_CTRL_SHDW
	global EMIF_DLL_CALIB_CTRL
	global EMIF_DLL_CALIB_CTRL_SHDW
	global EMIF_TEMP_ALERT_CONFIG

	mww $EMIF_PWR_MGMT_CTRL		0x00
	mww $EMIF_PWR_MGMT_CTRL_SHDW	0x00
	mww $EMIF_DLL_CALIB_CTRL	0x00050000
	mww $EMIF_DLL_CALIB_CTRL_SHDW	0x00050000
	mww $EMIF_TEMP_ALERT_CONFIG	0x00
}

proc config_ddr_priority { } {
	global EMIF_PRI_COS_MAP
	global EMIF_CONNID_COS_1_MAP
	global EMIF_CONNID_COS_2_MAP
	global EMIF_RD_WR_EXEC_THRSH
	global COS_CONFIG

	mww $EMIF_PRI_COS_MAP       0x00
	mww $EMIF_CONNID_COS_1_MAP  0x00
	mww $EMIF_CONNID_COS_2_MAP  0x0
	mww $EMIF_RD_WR_EXEC_THRSH  0x0405
	mww $COS_CONFIG             0x00ffffff
}

proc config_ddr3 { SDRAM_CONFIG } {
	global CM_DLL_CTRL
	global EMIF_IODFT_TLGC
	global EMIF_RDWR_LVL_CTRL
	global EMIF_RDWR_LVL_RMP_CTRL
	global EMIF_SDRAM_CONFIG
	global EMIF_SDRAM_CONFIG_EXT
	global EMIF_SDRAM_REF_CTRL
	global EMIF_SDRAM_REF_CTRL_SHDW
	global EMIF_STATUS
	global EXT_PHY_CTRL_36
	global EXT_PHY_CTRL_36_SHDW

	emif_prcm_clk_enable
	vtp_enable

	set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
	mww $CM_DLL_CTRL $dll
	while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }

	config_ddr_ioctrl

	mww $EMIF_SDRAM_CONFIG_EXT	0xc163
	mww $EMIF_IODFT_TLGC		0x2011
	mww $EMIF_IODFT_TLGC		0x2411
	mww $EMIF_IODFT_TLGC		0x2011
	mww $EMIF_SDRAM_REF_CTRL	0x80003000

	config_ddr_phy

	mww $EMIF_IODFT_TLGC		0x2011
	mww $EMIF_IODFT_TLGC		0x2411
	mww $EMIF_IODFT_TLGC		0x2011

	config_ddr_timing
	config_ddr_pm
	config_ddr_priority

	mww $EMIF_SDRAM_REF_CTRL	0x3000
	mww $EMIF_SDRAM_CONFIG		$SDRAM_CONFIG

	mww $EMIF_SDRAM_REF_CTRL	0x0c30
	mww $EMIF_SDRAM_REF_CTRL_SHDW	0x0c30

	sleep 10

	set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
	mww $EXT_PHY_CTRL_36		$tmp
	mww $EXT_PHY_CTRL_36_SHDW	$tmp

	mww $EMIF_RDWR_LVL_RMP_CTRL	0x80000000
	mww $EMIF_RDWR_LVL_CTRL		0x80000000

	while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }

	if { [ mrw $EMIF_STATUS ]  & 0x70 } {
		error "DDR3 Hardware Leveling incomplete!!!"
	}
}

proc init_platform { SDRAM_CONFIG } {
	config_opp100
	config_ddr3 $SDRAM_CONFIG
}

$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
$_TARGETNAME configure -event reset-end { disable_watchdog }