2022-08-01 18:38:09 -05:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2022-05-21 16:49:54 -05:00
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/***************************************************************************
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* Reset stub used by esp32 target *
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* Copyright (C) 2017 Espressif Systems Ltd. *
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***************************************************************************/
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#define RTC_CNTL_RESET_STATE_REG 0x3ff48034
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#define RTC_CNTL_RESET_STATE_DEF 0x3000
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#define RTC_CNTL_CLK_CONF_REG 0x3ff48070
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#define RTC_CNTL_CLK_CONF_DEF 0x2210
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#define RTC_CNTL_STORE4_REG 0x3ff480b0
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#define RTC_CNTL_STORE5_REG 0x3ff480b4
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#define WDT_WKEY_VALUE 0x50D83AA1
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#define TIMG0_WDTWPROTECT_REG 0x3ff5f064
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#define TIMG0_WDTCONFIG0_REG 0x3ff5f048
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#define TIMG1_WDTWPROTECT_REG 0x3FF60064
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#define TIMG1_WDTCONFIG0_REG 0x3ff60048
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#define RTC_CNTL_WDTCONFIG0_REG 0x3ff4808c
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#define RTC_CNTL_WDTWPROTECT_REG 0x3ff480a4
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#define JTAG_ENABLE_REG 0x3ff5a1fc
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#define RTC_CNTL_OPTIONS0_REG 0x3ff48000
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#define RTC_CNTL_OPTIONS0_DEF 0x1c492000
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#define RTC_CNTL_SW_SYS_RST 0x80000000
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#define DPORT_APPCPU_CTRL_A_REG 0x3ff0002c
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#define DPORT_APPCPU_RST_EN 0x1
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#define DPORT_APPCPU_CTRL_B_REG 0x3ff00030
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#define DPORT_APPCPU_CLKGATE_EN 0x1
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#define DPORT_APPCPU_CTRL_C_REG 0x3ff00034
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#define DPORT_APPCPU_CTRL_D_REG 0x3ff00038
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/* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
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* it instead of the ROM code (0x40000400). This stub disables watchdogs and
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* goes into a loop.
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* OpenOCD will then halt the target and perform CPU reset using OCD.
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*/
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/* Has to be at offset 0. This is the entry point of the CPU, once
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* RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
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* CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
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*/
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.global cpu_at_start_handler
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.type cpu_at_start_handler,@function
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.align 4
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cpu_at_start_handler:
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j start
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/* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
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* memory, OpenOCD will set the PC to this address, and resume execution.
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* The stub will then jump to 'reset' label and perform the reset.
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*/
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.global cpu_reset_handler
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.type cpu_reset_handler,@function
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.align 4
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cpu_reset_handler:
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j reset
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.align 4
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.literal_position
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.align 4
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reset:
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/* Use a5 as a zero register */
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xor a5, a5, a5
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/* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
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movi a4, RTC_CNTL_RESET_STATE_REG
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s32i a5, a4, 0
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/* Set some clock-related RTC registers to the default values */
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movi a4, RTC_CNTL_STORE4_REG
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s32i a5, a4, 0
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movi a4, RTC_CNTL_STORE5_REG
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s32i a5, a4, 0
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movi a4, RTC_CNTL_CLK_CONF_REG
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movi a3, RTC_CNTL_CLK_CONF_DEF
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s32i a3, a4, 0
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/* Reset the digital part of the chip (RTC controller doesn't get reset) */
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movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
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movi a4, RTC_CNTL_OPTIONS0_REG
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s32i a3, a4, 0
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/* Doesn't reach beyond this instruction */
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.align 4
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start:
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/* If running on the APP CPU, skip directly to the parking loop */
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rsr.prid a6
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extui a6, a6, 1, 1
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bnez a6, parking_loop
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/* Use a5 as a zero register */
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xor a5, a5, a5
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/* Disable the watchdogs */
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movi a3, WDT_WKEY_VALUE
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movi a4, RTC_CNTL_WDTWPROTECT_REG
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s32i.n a3, a4, 0
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movi a4, TIMG0_WDTWPROTECT_REG
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s32i.n a3, a4, 0
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movi a4, TIMG1_WDTWPROTECT_REG
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s32i.n a3, a4, 0
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movi a4, RTC_CNTL_WDTCONFIG0_REG
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s32i.n a5, a4, 0
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movi a4, TIMG0_WDTCONFIG0_REG
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s32i.n a5, a4, 0
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movi a4, TIMG1_WDTCONFIG0_REG
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s32i.n a5, a4, 0
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/* Enable JTAG (needed since rev. 3) */
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movi a4, JTAG_ENABLE_REG
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s32i.n a5, a4, 0
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/* Clear APP_CPU boot address */
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movi a4, DPORT_APPCPU_CTRL_D_REG
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s32i.n a5, a4, 0
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/* Clear APP_CPU clock gating */
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movi a4, DPORT_APPCPU_CTRL_B_REG
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movi a3, DPORT_APPCPU_CLKGATE_EN
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s32i.n a3, a4, 0
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/* Set and clear APP_CPU reset */
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movi a4, DPORT_APPCPU_CTRL_A_REG
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movi a3, DPORT_APPCPU_RST_EN
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s32i.n a3, a4, 0
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s32i.n a5, a4, 0
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/* Restore the reset vector to ROM */
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movi a4, RTC_CNTL_RESET_STATE_REG
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movi a3, RTC_CNTL_RESET_STATE_DEF
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s32i.n a3, a4, 0
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parking_loop:
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/* PRO and APP CPU will be in this loop, until OpenOCD
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* finds the JTAG taps and puts the CPUs into debug mode.
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*/
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waiti 0
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j parking_loop
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