2022-08-30 15:18:31 -05:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface
- write speed up to 150 kByte/s on STM32F469I-disco (due to
SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
(tested only in single/quad mode as most devices either don't
support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
(superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
and single 8-line modes, (not in hyper flash mode)
Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.
Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
2016-12-21 03:35:58 -06:00
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/***************************************************************************
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* Copyright (C) 2019 by Andreas Bolsch *
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* andreas.bolsch@mni.thm.de *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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/* Params:
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* r0 - total count (bytes), crc32 (out)
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* r1 - flash page size
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* r2 - address offset into flash
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* r3 - OCTOSPI io_base
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* Clobbered:
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* r4 - tmp
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* r5 - address of OCTOSPI_DR
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* r6 - address of OCTOSPI_CCR
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* r7 - tmp
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*/
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#include "../../../../src/flash/nor/stmqspi.h"
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#define OCTOSPI_CCR_CCR (OCTOSPI_CCR - OCTOSPI_CCR)
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#define OCTOSPI_TCR_CCR (OCTOSPI_TCR - OCTOSPI_CCR)
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#define OCTOSPI_IR_CCR (OCTOSPI_IR - OCTOSPI_CCR)
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.macro octospi_abort
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movs r5, #(1<<SPI_ABORT) /* abort bit mask */
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ldr r7, [r3, #OCTOSPI_CR] /* get OCTOSPI CR register */
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orrs r7, r7, r5 /* set abort bit */
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str r7, [r3, #OCTOSPI_CR] /* store new CR register */
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.endm
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.macro wait_busy
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0:
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ldr r7, [r3, #OCTOSPI_SR] /* load status */
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lsrs r7, r7, #(SPI_BUSY+1) /* shift BUSY into C */
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bcs 0b /* loop until BUSY cleared */
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movs r7, #(1<<SPI_TCF) /* TCF bitmask */
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str r7, [r3, #OCTOSPI_FCR] /* clear TCF flag */
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.endm
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start:
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subs r0, r0, #1 /* decrement count for DLR */
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subs r1, r1, #1 /* page size mask and for DLR */
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movs r4, #0x00 /* initialize crc */
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mvns r4, r4 /* to 0xFFFFFFFF */
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start_read:
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octospi_abort /* start in clean state */
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movs r5, #OCTOSPI_DR /* load OCTOSPI_DR address offset */
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adds r5, r5, r3 /* address of OCTOSPI_DR */
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movs r6, #OCTOSPI_CCR-OCTOSPI_DR /* load OCTOSPI_CCR address offset */
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adds r6, r6, r5 /* address of OCTOSPI_CCR */
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wait_busy
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ldr r7, cr_page_read /* indirect read mode */
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str r7, [r3, #OCTOSPI_CR] /* set mode */
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mov r7, r2 /* get current start address */
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orrs r7, r7, r1 /* end of current page */
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subs r7, r7, r2 /* count-1 to end of page */
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cmp r7, r0 /* if this count <= remaining */
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bls write_dlr /* then read to end of page */
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mov r7, r0 /* else read all remaining */
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write_dlr:
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str r7, [r3, #OCTOSPI_DLR] /* size-1 in DLR register */
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ldr r7, ccr_page_read /* CCR for read */
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str r7, [r6, #OCTOSPI_CCR_CCR] /* initiate transfer */
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ldr r7, tcr_page_read /* TCR for read */
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str r7, [r6, #OCTOSPI_TCR_CCR] /* instruction */
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ldr r7, ir_page_read /* IR for read */
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str r7, [r6, #OCTOSPI_IR_CCR] /* instruction */
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str r2, [r3, #OCTOSPI_AR] /* store SPI start address */
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ldr r6, =0x04C11DB7 /* CRC32 polynomial */
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read_loop:
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ldrb r7, [r5] /* read next byte from DR */
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lsls r7, r7, #24 /* shift into msb */
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eors r4, r4, r7
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.rept 8 /* unrolled bit loop */
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asrs r7, r4, #31 /* copy bit 31 into bits 0 to 31 */
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ands r7, r7, r6 /* r7 neg. -> CRC32XOR, pos. -> 0x0 */
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lsls r4, r4, #1 /* shift result */
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eors r4, r4, r7 /* eor by CRC32XOR or 0x0 */
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.endr
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adds r2, r2, #1 /* increment address */
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subs r0, r0, #1 /* decrement (count-1) */
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bmi exit /* stop if no data left */
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tst r2, r1 /* page end ? */
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bne read_loop /* if not, then next byte */
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page_end:
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bal start_read /* then next page */
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.pool
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exit:
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mvns r0, r4 /* invert to get final result */
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octospi_abort /* to idle state */
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.align 2 /* align to word, bkpt is 4 words */
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bkpt #0 /* before code end for exit_point */
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.align 2 /* align to word */
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cr_page_read:
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.space 4 /* OCTOSPI_CR value for read command */
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ccr_page_read:
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.space 4 /* OCTOSPI_CCR value for read command */
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tcr_page_read:
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.space 4 /* OCTOSPI_TCR value for read command */
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ir_page_read:
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.space 4 /* OCTOSPI_IR value for read command */
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