riscv-openocd/contrib/loaders/flash/stmqspi/stmoctospi_crc32.S

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/* SPDX-License-Identifier: GPL-2.0-or-later */
Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface - write speed up to 150 kByte/s on STM32F469I-disco (due to SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in dual 4-line mode or STM32H73BI-Disco in octal mode - tested with STM32L476G-disco (64MBit flash, 3-byte addr), STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and STM32L476G-Disco (all 128Mbit flash, 3-byte addr), STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr) STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr) STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr) STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr) - suitable cfg for Discovery boards included - limited parsing of SFDP data if flash device not hardcoded (tested only in single/quad mode as most devices either don't support SFDP at all or have empty(!) SFDP memory) - 'set' command for auto detection override (e. g. for EEPROMs) - 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.) - makefile for creation of binary loader files - tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg - tcl/board/stm32f7discovery.cfg removed as name is ambiguous (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg) - dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI with two W25Q128FV, sample cfg files included and on STM32H745I-Disco, STM32H747I-Disco, STM32H750B-Disco - read/verify/erase_check uses indirect read mode to work around silicon bug in H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last bytes causes debug interface to hang) - octospi supported only in single/dual 1-line, 2-line, 4-line and single 8-line modes, (not in hyper flash mode) Requirements: GPIOs must be initialized appropriately, and SPI flash chip be configured appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip specific, cf. included cfg files. The driver infers most parameters from current setting in CR, CCR, ... registers. Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4321 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com>
2016-12-21 03:35:58 -06:00
/***************************************************************************
* Copyright (C) 2019 by Andreas Bolsch *
* andreas.bolsch@mni.thm.de *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Params:
* r0 - total count (bytes), crc32 (out)
* r1 - flash page size
* r2 - address offset into flash
* r3 - OCTOSPI io_base
* Clobbered:
* r4 - tmp
* r5 - address of OCTOSPI_DR
* r6 - address of OCTOSPI_CCR
* r7 - tmp
*/
#include "../../../../src/flash/nor/stmqspi.h"
#define OCTOSPI_CCR_CCR (OCTOSPI_CCR - OCTOSPI_CCR)
#define OCTOSPI_TCR_CCR (OCTOSPI_TCR - OCTOSPI_CCR)
#define OCTOSPI_IR_CCR (OCTOSPI_IR - OCTOSPI_CCR)
.macro octospi_abort
movs r5, #(1<<SPI_ABORT) /* abort bit mask */
ldr r7, [r3, #OCTOSPI_CR] /* get OCTOSPI CR register */
orrs r7, r7, r5 /* set abort bit */
str r7, [r3, #OCTOSPI_CR] /* store new CR register */
.endm
.macro wait_busy
0:
ldr r7, [r3, #OCTOSPI_SR] /* load status */
lsrs r7, r7, #(SPI_BUSY+1) /* shift BUSY into C */
bcs 0b /* loop until BUSY cleared */
movs r7, #(1<<SPI_TCF) /* TCF bitmask */
str r7, [r3, #OCTOSPI_FCR] /* clear TCF flag */
.endm
start:
subs r0, r0, #1 /* decrement count for DLR */
subs r1, r1, #1 /* page size mask and for DLR */
movs r4, #0x00 /* initialize crc */
mvns r4, r4 /* to 0xFFFFFFFF */
start_read:
octospi_abort /* start in clean state */
movs r5, #OCTOSPI_DR /* load OCTOSPI_DR address offset */
adds r5, r5, r3 /* address of OCTOSPI_DR */
movs r6, #OCTOSPI_CCR-OCTOSPI_DR /* load OCTOSPI_CCR address offset */
adds r6, r6, r5 /* address of OCTOSPI_CCR */
wait_busy
ldr r7, cr_page_read /* indirect read mode */
str r7, [r3, #OCTOSPI_CR] /* set mode */
mov r7, r2 /* get current start address */
orrs r7, r7, r1 /* end of current page */
subs r7, r7, r2 /* count-1 to end of page */
cmp r7, r0 /* if this count <= remaining */
bls write_dlr /* then read to end of page */
mov r7, r0 /* else read all remaining */
write_dlr:
str r7, [r3, #OCTOSPI_DLR] /* size-1 in DLR register */
ldr r7, ccr_page_read /* CCR for read */
str r7, [r6, #OCTOSPI_CCR_CCR] /* initiate transfer */
ldr r7, tcr_page_read /* TCR for read */
str r7, [r6, #OCTOSPI_TCR_CCR] /* instruction */
ldr r7, ir_page_read /* IR for read */
str r7, [r6, #OCTOSPI_IR_CCR] /* instruction */
str r2, [r3, #OCTOSPI_AR] /* store SPI start address */
ldr r6, =0x04C11DB7 /* CRC32 polynomial */
read_loop:
ldrb r7, [r5] /* read next byte from DR */
lsls r7, r7, #24 /* shift into msb */
eors r4, r4, r7
.rept 8 /* unrolled bit loop */
asrs r7, r4, #31 /* copy bit 31 into bits 0 to 31 */
ands r7, r7, r6 /* r7 neg. -> CRC32XOR, pos. -> 0x0 */
lsls r4, r4, #1 /* shift result */
eors r4, r4, r7 /* eor by CRC32XOR or 0x0 */
.endr
adds r2, r2, #1 /* increment address */
subs r0, r0, #1 /* decrement (count-1) */
bmi exit /* stop if no data left */
tst r2, r1 /* page end ? */
bne read_loop /* if not, then next byte */
page_end:
bal start_read /* then next page */
.pool
exit:
mvns r0, r4 /* invert to get final result */
octospi_abort /* to idle state */
.align 2 /* align to word, bkpt is 4 words */
bkpt #0 /* before code end for exit_point */
.align 2 /* align to word */
cr_page_read:
.space 4 /* OCTOSPI_CR value for read command */
ccr_page_read:
.space 4 /* OCTOSPI_CCR value for read command */
tcr_page_read:
.space 4 /* OCTOSPI_TCR value for read command */
ir_page_read:
.space 4 /* OCTOSPI_IR value for read command */