2022-08-30 10:01:12 -05:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2022-08-30 17:20:16 -05:00
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2021-11-08 11:26:51 -06:00
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "../../../../src/flash/nor/spi.h"
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/* Register offsets */
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#define FESPI_REG_SCKDIV 0x00
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#define FESPI_REG_SCKMODE 0x04
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#define FESPI_REG_CSID 0x10
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#define FESPI_REG_CSDEF 0x14
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#define FESPI_REG_CSMODE 0x18
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#define FESPI_REG_DCSSCK 0x28
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#define FESPI_REG_DSCKCS 0x2a
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#define FESPI_REG_DINTERCS 0x2c
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#define FESPI_REG_DINTERXFR 0x2e
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#define FESPI_REG_FMT 0x40
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#define FESPI_REG_TXFIFO 0x48
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#define FESPI_REG_RXFIFO 0x4c
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#define FESPI_REG_TXCTRL 0x50
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#define FESPI_REG_RXCTRL 0x54
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#define FESPI_REG_FCTRL 0x60
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#define FESPI_REG_FFMT 0x64
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#define FESPI_REG_IE 0x70
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#define FESPI_REG_IP 0x74
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/* Fields */
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#define FESPI_SCK_POL 0x1
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#define FESPI_SCK_PHA 0x2
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#define FESPI_FMT_PROTO(x) ((x) & 0x3)
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#define FESPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
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#define FESPI_FMT_DIR(x) (((x) & 0x1) << 3)
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#define FESPI_FMT_LEN(x) (((x) & 0xf) << 16)
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/* TXCTRL register */
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#define FESPI_TXWM(x) ((x) & 0xffff)
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/* RXCTRL register */
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#define FESPI_RXWM(x) ((x) & 0xffff)
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#define FESPI_IP_TXWM 0x1
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#define FESPI_IP_RXWM 0x2
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#define FESPI_FCTRL_EN 0x1
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#define FESPI_INSN_CMD_EN 0x1
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#define FESPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
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#define FESPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
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#define FESPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
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#define FESPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
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#define FESPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
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#define FESPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
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#define FESPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
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/* Values */
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#define FESPI_CSMODE_AUTO 0
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#define FESPI_CSMODE_HOLD 2
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#define FESPI_CSMODE_OFF 3
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#define FESPI_DIR_RX 0
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#define FESPI_DIR_TX 1
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#define FESPI_PROTO_S 0
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#define FESPI_PROTO_D 1
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#define FESPI_PROTO_Q 2
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#define FESPI_ENDIAN_MSB 0
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#define FESPI_ENDIAN_LSB 1
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/* Timeouts we use, in number of status checks. */
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#define TIMEOUT 1000
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/* #define DEBUG to make the return error codes provide enough information to
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* reconstruct the stack from where the error occurred. This is not enabled
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* usually to reduce the program size. */
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#ifdef DEBUG
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#define ERROR_STACK(x) (x)
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#define ERROR_FESPI_TXWM_WAIT 0x10
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#define ERROR_FESPI_TX 0x100
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#define ERROR_FESPI_RX 0x1000
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#define ERROR_FESPI_WIP 0x50000
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#else
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#define ERROR_STACK(x) 0
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#define ERROR_FESPI_TXWM_WAIT 1
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#define ERROR_FESPI_TX 1
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#define ERROR_FESPI_RX 1
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#define ERROR_FESPI_WIP 1
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#endif
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#define ERROR_OK 0
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static int fespi_txwm_wait(volatile uint32_t *ctrl_base);
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static void fespi_disable_hw_mode(volatile uint32_t *ctrl_base);
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static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base);
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static int fespi_wip(volatile uint32_t *ctrl_base);
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static int fespi_write_buffer(volatile uint32_t *ctrl_base,
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const uint8_t *buffer, unsigned offset, unsigned len,
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uint32_t flash_info);
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/* Can set bits 3:0 in result. */
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/* flash_info contains:
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* bits 7:0 -- pprog_cmd
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* bit 8 -- 0 means send 3 bytes after pprog_cmd, 1 means send 4 bytes
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* after pprog_cmd
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*/
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int flash_fespi(volatile uint32_t *ctrl_base, uint32_t page_size,
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const uint8_t *buffer, unsigned offset, uint32_t count,
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uint32_t flash_info)
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{
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int result;
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result = fespi_txwm_wait(ctrl_base);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x1);
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/* Disable Hardware accesses*/
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fespi_disable_hw_mode(ctrl_base);
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/* poll WIP */
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result = fespi_wip(ctrl_base);
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if (result != ERROR_OK) {
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result |= ERROR_STACK(0x2);
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goto err;
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}
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/* Assume page_size is a power of two so we don't need the modulus code. */
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uint32_t page_offset = offset & (page_size - 1);
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/* central part, aligned words */
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while (count > 0) {
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uint32_t cur_count;
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/* clip block at page boundary */
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if (page_offset + count > page_size)
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cur_count = page_size - page_offset;
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else
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cur_count = count;
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result = fespi_write_buffer(ctrl_base, buffer, offset, cur_count, flash_info);
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if (result != ERROR_OK) {
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result |= ERROR_STACK(0x3);
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goto err;
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}
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page_offset = 0;
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buffer += cur_count;
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offset += cur_count;
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count -= cur_count;
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}
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err:
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/* Switch to HW mode before return to prompt */
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fespi_enable_hw_mode(ctrl_base);
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return result;
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}
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static uint32_t fespi_read_reg(volatile uint32_t *ctrl_base, unsigned address)
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{
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return ctrl_base[address / 4];
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}
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static void fespi_write_reg(volatile uint32_t *ctrl_base, unsigned address, uint32_t value)
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{
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ctrl_base[address / 4] = value;
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}
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static void fespi_disable_hw_mode(volatile uint32_t *ctrl_base)
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{
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uint32_t fctrl = fespi_read_reg(ctrl_base, FESPI_REG_FCTRL);
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fespi_write_reg(ctrl_base, FESPI_REG_FCTRL, fctrl & ~FESPI_FCTRL_EN);
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}
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static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base)
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{
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uint32_t fctrl = fespi_read_reg(ctrl_base, FESPI_REG_FCTRL);
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fespi_write_reg(ctrl_base, FESPI_REG_FCTRL, fctrl | FESPI_FCTRL_EN);
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}
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/* Can set bits 7:4 in result. */
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static int fespi_txwm_wait(volatile uint32_t *ctrl_base)
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{
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unsigned timeout = TIMEOUT;
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while (timeout--) {
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uint32_t ip = fespi_read_reg(ctrl_base, FESPI_REG_IP);
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if (ip & FESPI_IP_TXWM)
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return ERROR_OK;
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}
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return ERROR_FESPI_TXWM_WAIT;
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}
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static void fespi_set_dir(volatile uint32_t *ctrl_base, bool dir)
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{
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uint32_t fmt = fespi_read_reg(ctrl_base, FESPI_REG_FMT);
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fespi_write_reg(ctrl_base, FESPI_REG_FMT,
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(fmt & ~(FESPI_FMT_DIR(0xFFFFFFFF))) | FESPI_FMT_DIR(dir));
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}
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/* Can set bits 11:8 in result. */
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static int fespi_tx(volatile uint32_t *ctrl_base, uint8_t in)
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{
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unsigned timeout = TIMEOUT;
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while (timeout--) {
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uint32_t txfifo = fespi_read_reg(ctrl_base, FESPI_REG_TXFIFO);
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if (!(txfifo >> 31)) {
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fespi_write_reg(ctrl_base, FESPI_REG_TXFIFO, in);
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return ERROR_OK;
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}
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}
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return ERROR_FESPI_TX;
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}
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/* Can set bits 15:12 in result. */
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static int fespi_rx(volatile uint32_t *ctrl_base, uint8_t *out)
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{
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unsigned timeout = TIMEOUT;
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while (timeout--) {
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uint32_t value = fespi_read_reg(ctrl_base, FESPI_REG_RXFIFO);
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if (!(value >> 31)) {
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if (out)
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*out = value & 0xff;
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return ERROR_OK;
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}
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}
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return ERROR_FESPI_RX;
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}
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/* Can set bits 19:16 in result. */
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static int fespi_wip(volatile uint32_t *ctrl_base)
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{
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fespi_set_dir(ctrl_base, FESPI_DIR_RX);
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fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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int result = fespi_tx(ctrl_base, SPIFLASH_READ_STATUS);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x10000);
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result = fespi_rx(ctrl_base, NULL);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x20000);
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unsigned timeout = TIMEOUT;
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while (timeout--) {
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result = fespi_tx(ctrl_base, 0);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x30000);
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uint8_t rx;
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result = fespi_rx(ctrl_base, &rx);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x40000);
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if ((rx & SPIFLASH_BSY_BIT) == 0) {
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fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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fespi_set_dir(ctrl_base, FESPI_DIR_TX);
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return ERROR_OK;
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}
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}
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return ERROR_FESPI_WIP;
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}
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/* Can set bits 23:20 in result. */
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static int fespi_write_buffer(volatile uint32_t *ctrl_base,
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const uint8_t *buffer, unsigned offset, unsigned len,
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uint32_t flash_info)
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{
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int result = fespi_tx(ctrl_base, SPIFLASH_WRITE_ENABLE);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x100000);
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result = fespi_txwm_wait(ctrl_base);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x200000);
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fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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result = fespi_tx(ctrl_base, flash_info & 0xff);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x300000);
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if (flash_info & 0x100) {
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result = fespi_tx(ctrl_base, offset >> 24);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x400000);
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}
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result = fespi_tx(ctrl_base, offset >> 16);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x400000);
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result = fespi_tx(ctrl_base, offset >> 8);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x500000);
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result = fespi_tx(ctrl_base, offset);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x600000);
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for (unsigned i = 0; i < len; i++) {
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result = fespi_tx(ctrl_base, buffer[i]);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x700000);
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}
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result = fespi_txwm_wait(ctrl_base);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x800000);
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fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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result = fespi_wip(ctrl_base);
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if (result != ERROR_OK)
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return result | ERROR_STACK(0x900000);
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return ERROR_OK;
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}
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