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riscv-openocd/contrib/loaders/flash/fespi/riscv64_fespi.inc

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Redo fespi flash algorithm (#384) * WIP, rewrite of flash algorithm. Just put all the flashing logic into the algorithm, instead of using an intermediate format. This should reduce total data written while flashing by about 9%, and also makes the code much simpler. Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79 * New algorithm works. Speeds up Arty flashing another 9%. wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s) verified 2192012 bytes in 6.693336s (319.816 KiB/s) 8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4 * Fix whitespace. Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b * Don't reserve so much stack space. Also properly check XLEN in riscv_wrapper.S. Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
2019-07-09 12:05:07 -05:00
/* Autogenerated with ../../../../src/helper/bin2char.sh */
fespi: Properly support large flash devices (#421) * 64-bit progbuf memory reads work. Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399 * 64-bit writes work. Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23 * Let targets indicate number of supported data bits. This is used by the default memory read/write functions when creating an aligned block. I'm adding this mainly to ensure I get coverage of the 64-bit progbuf memory read/write code. Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b * Make mingw32 happy. Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916 * WIP >16MB flashing. Change-Id: Ibef9244f8573d2fbf19b80e5db7c2d3a10da59b5 * >16MB flashing works on Hi5 Unleashed But now flashing HiFive1 is broken. Change-Id: If939c9e21cf793ae727f3335205abd261a998c0c * Fix off-by-one error on bank size. Change-Id: I0e6e49db8c1bfddb2c5f67d40f62111246db8dcb * Fix formatting. Change-Id: I4211f9328c7d11ea659be9588a81aa2cd59017f9
2019-11-15 14:50:08 -06:00
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Redo fespi flash algorithm (#384) * WIP, rewrite of flash algorithm. Just put all the flashing logic into the algorithm, instead of using an intermediate format. This should reduce total data written while flashing by about 9%, and also makes the code much simpler. Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79 * New algorithm works. Speeds up Arty flashing another 9%. wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s) verified 2192012 bytes in 6.693336s (319.816 KiB/s) 8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4 * Fix whitespace. Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b * Don't reserve so much stack space. Also properly check XLEN in riscv_wrapper.S. Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
2019-07-09 12:05:07 -05:00
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Fix flashing HiFive Unleashed (#402) * Align algorithm stack to XLEN. This fixes algorithm timeout on RV64 targets. Also improve debug information in various places. Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d * Compile 32-bit RISC-V algorithms for RV32E. Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa * Remove debug code. Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b * Dump start of gdb packets escaping non-printable. Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915 * Propagate flash programming errors. Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7 * Improve debug messaging. Change-Id: I47ac3518f3b241986c677824864102936100adf6 * Add debug output to flash image. This is helpful when you're debugging the flash algorithm itself, and a nop when running it through OpenOCD. Change-Id: Id44c6498c288872cc2cec79044116ac38198c572 * Make timeout depend on how much data is written. Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e * Fix issi erase commands. This is required to flash HiFive Unleashed. Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10 * Fix running algorithm on multicore `-rtos riscv`. The bug was that poll() might change the currently selected hart, and in that case we'd access registers on that other hart after the algorithm is finished. Change-Id: I140431898285cf471b372139cef2378ab4879377 * Make fespi flash algorithm debugging optional. Also add a scheme that allows you to see the stack trace of where a failure occurred if debugging is enabled. Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-09 14:01:17 -05:00
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fespi: Properly support large flash devices (#421) * 64-bit progbuf memory reads work. Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399 * 64-bit writes work. Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23 * Let targets indicate number of supported data bits. This is used by the default memory read/write functions when creating an aligned block. I'm adding this mainly to ensure I get coverage of the 64-bit progbuf memory read/write code. Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b * Make mingw32 happy. Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916 * WIP >16MB flashing. Change-Id: Ibef9244f8573d2fbf19b80e5db7c2d3a10da59b5 * >16MB flashing works on Hi5 Unleashed But now flashing HiFive1 is broken. Change-Id: If939c9e21cf793ae727f3335205abd261a998c0c * Fix off-by-one error on bank size. Change-Id: I0e6e49db8c1bfddb2c5f67d40f62111246db8dcb * Fix formatting. Change-Id: I4211f9328c7d11ea659be9588a81aa2cd59017f9
2019-11-15 14:50:08 -06:00
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