2022-08-30 15:18:31 -05:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2014-06-27 01:13:24 -05:00
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/***************************************************************************
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* Copyright (C) 2014 by Angus Gratton *
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* Derived from stm32f1x.S:
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* Copyright (C) 2011 by Andreas Fritiofson *
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* andreas.fritiofson@gmail.com *
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* Copyright (C) 2013 by Roman Dmitrienko *
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* me@iamroman.org *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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/* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
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* very generic (CPU blocks during flash writes), so this is actually
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2016-05-14 13:21:49 -05:00
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* just a generic word-oriented copy routine for Cortex-M0 (also
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* suitable for Cortex-M0+/M3/M4.)
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2014-06-27 01:13:24 -05:00
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*
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* To assemble:
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* arm-none-eabi-gcc -c cortex-m0.S
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*
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* To disassemble:
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* arm-none-eabi-objdump -o cortex-m0.o
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*
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* Thanks to Jens Bauer for providing advice on some of the tweaks.
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*/
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/* Params:
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* r0 - byte count (in)
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* r1 - workarea start
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* r2 - workarea end
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* r3 - target address
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* Clobbered:
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* r4 - rp
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* r5 - wp, tmp
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*/
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wait_fifo:
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ldr r5, [r1, #0] /* read wp */
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cmp r5, #0 /* abort if wp == 0 */
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beq exit
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ldr r4, [r1, #4] /* read rp */
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cmp r4, r5 /* wait until rp != wp */
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beq wait_fifo
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ldmia r4!, {r5} /* "*target_address++ = *rp++" */
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stmia r3!, {r5}
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cmp r4, r2 /* wrap rp at end of work area buffer */
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bcc no_wrap
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mov r4, r1
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adds r4, #8 /* skip rp,wp at start of work area */
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no_wrap:
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str r4, [r1, #4] /* write back rp */
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subs r0, #4 /* decrement byte count */
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bne wait_fifo /* loop if not done */
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exit:
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bkpt #0
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