2022-08-30 10:01:12 -05:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2022-08-30 15:18:31 -05:00
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2008-04-24 06:09:28 -05:00
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/***************************************************************************
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* Copyright (C) 2007 by Pavel Chromy *
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* chromy@asix.cz *
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***************************************************************************/
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#include "samflash.h"
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2009-06-23 17:42:54 -05:00
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unsigned int flash_page_count = 1024;
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unsigned int flash_page_size = 256;
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2008-04-24 06:09:28 -05:00
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/* pages per lock bit */
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2009-06-23 17:42:54 -05:00
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unsigned int flash_lock_pages = 1024/16;
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2008-04-24 06:09:28 -05:00
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/* detect chip and set loader parameters */
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int flash_init(void)
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{
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unsigned int nvpsiz;
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2009-06-23 17:42:54 -05:00
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nvpsiz = (inr(DBGU_CIDR) >> 8)&0xf;
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2008-04-24 06:09:28 -05:00
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switch (nvpsiz) {
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case 3:
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/* AT91SAM7x32 */
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2009-06-23 17:42:54 -05:00
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flash_page_count = 256;
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flash_page_size = 128;
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flash_lock_pages = 256/8;
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2008-04-24 06:09:28 -05:00
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break;
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case 5:
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/* AT91SAM7x64 */
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2009-06-23 17:42:54 -05:00
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flash_page_count = 512;
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flash_page_size = 128;
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flash_lock_pages = 512/16;
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2008-04-24 06:09:28 -05:00
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break;
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case 7:
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/* AT91SAM7x128*/
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2009-06-23 17:42:54 -05:00
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flash_page_count = 512;
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flash_page_size = 256;
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flash_lock_pages = 512/8;
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2008-04-24 06:09:28 -05:00
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break;
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case 9:
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/* AT91SAM7x256 */
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2009-06-23 17:42:54 -05:00
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flash_page_count = 1024;
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flash_page_size = 256;
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flash_lock_pages = 1024/16;
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2008-04-24 06:09:28 -05:00
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break;
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case 10:
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/* AT91SAM7x512 */
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2009-06-23 17:42:54 -05:00
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flash_page_count = 2048;
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flash_page_size = 256;
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flash_lock_pages = 2048/32;
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2008-04-24 06:09:28 -05:00
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break;
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default:
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return FLASH_STAT_INITE;
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}
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return FLASH_STAT_OK;
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}
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/* program single flash page */
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int flash_page_program(uint32 *data, int page_num)
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{
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int i;
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int efc_ofs;
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uint32 *flash_ptr;
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uint32 *data_ptr;
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/* select proper controller */
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2009-06-23 17:42:54 -05:00
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if (page_num >= 1024) efc_ofs = 0x10;
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else efc_ofs = 0;
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2008-04-24 06:09:28 -05:00
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/* wait until FLASH is ready, just for sure */
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2009-06-23 17:44:17 -05:00
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while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
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2008-04-24 06:09:28 -05:00
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/* calculate page address, only lower 8 bits are used to address the latch,
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but the upper part of address is needed for writing to proper EFC */
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2009-06-23 17:44:17 -05:00
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flash_ptr = (uint32 *)(FLASH_AREA_ADDR + (page_num*flash_page_size));
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2009-06-23 17:42:54 -05:00
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data_ptr = data;
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2008-04-24 06:09:28 -05:00
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/* copy data to latch */
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2009-06-23 17:42:54 -05:00
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for (i = flash_page_size/4; i; i--) {
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/* we do not use memcpy to be sure that only 32 bit access is used */
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*(flash_ptr++)=*(data_ptr++);
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}
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/* page number and page write command to FCR */
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2009-06-23 17:44:17 -05:00
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outr(MC_FCR + efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
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2008-04-24 06:09:28 -05:00
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/* wait until it's done */
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2009-06-23 17:44:17 -05:00
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while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
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2008-04-24 06:09:28 -05:00
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/* check for errors */
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2009-06-23 17:44:17 -05:00
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if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
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if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
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2008-04-24 06:09:28 -05:00
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#if 0
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/* verify written data */
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2009-06-23 17:44:17 -05:00
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flash_ptr = (uint32 *)(FLASH_AREA_ADDR + (page_num*flash_page_size));
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2009-06-23 17:42:54 -05:00
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data_ptr = data;
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2008-04-24 06:09:28 -05:00
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2009-06-23 17:42:54 -05:00
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for (i = flash_page_size/4; i; i--) {
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2008-04-24 06:09:28 -05:00
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if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;
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}
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#endif
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return FLASH_STAT_OK;
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}
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int flash_erase_plane(int efc_ofs)
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{
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unsigned int lockbits;
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int page_num;
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2009-06-23 17:42:54 -05:00
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page_num = 0;
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2009-06-23 17:44:17 -05:00
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lockbits = inr(MC_FSR + efc_ofs) >> 16;
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2008-04-24 06:09:28 -05:00
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while (lockbits) {
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if (lockbits&1) {
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/* wait until FLASH is ready, just for sure */
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2009-06-23 17:44:17 -05:00
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while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
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2008-04-24 06:09:28 -05:00
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2009-06-23 17:44:17 -05:00
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outr(MC_FCR + efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
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2008-04-24 06:09:28 -05:00
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/* wait until it's done */
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2009-06-23 17:44:17 -05:00
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while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
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2008-04-24 06:09:28 -05:00
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/* check for errors */
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2009-06-23 17:44:17 -05:00
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if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
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if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
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2008-04-24 06:09:28 -05:00
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}
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2009-06-23 17:45:47 -05:00
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if ((page_num += flash_lock_pages) > flash_page_count) break;
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2008-04-24 06:09:28 -05:00
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lockbits>>=1;
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}
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/* wait until FLASH is ready, just for sure */
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2009-06-23 17:44:17 -05:00
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while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
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2008-04-24 06:09:28 -05:00
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/* erase all command to FCR */
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2009-06-23 17:44:17 -05:00
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outr(MC_FCR + efc_ofs, 0x5a000008);
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2008-04-24 06:09:28 -05:00
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/* wait until it's done */
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2009-06-23 17:44:17 -05:00
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while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
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2008-04-24 06:09:28 -05:00
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/* check for errors */
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2009-06-23 17:44:17 -05:00
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if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
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if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
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2008-04-24 06:09:28 -05:00
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/* set no erase before programming */
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2009-06-23 17:45:15 -05:00
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outr(MC_FMR + efc_ofs, inr(MC_FMR + efc_ofs) | 0x80);
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2008-04-24 06:09:28 -05:00
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return FLASH_STAT_OK;
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}
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/* erase whole chip */
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int flash_erase_all(void)
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{
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int result;
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2009-06-23 17:49:23 -05:00
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2009-06-23 17:42:54 -05:00
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if ((result = flash_erase_plane(0)) != FLASH_STAT_OK) return result;
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2008-04-24 06:09:28 -05:00
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/* the second flash controller, if any */
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2009-06-23 17:45:47 -05:00
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if (flash_page_count > 1024) result = flash_erase_plane(0x10);
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2008-04-24 06:09:28 -05:00
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return result;
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}
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int flash_verify(uint32 adr, unsigned int len, uint8 *src)
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{
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unsigned char *flash_ptr;
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2009-06-23 17:44:17 -05:00
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flash_ptr = (uint8 *)FLASH_AREA_ADDR + adr;
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2009-06-23 17:46:23 -05:00
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for (;len; len--) {
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2008-04-24 06:09:28 -05:00
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if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;
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}
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return FLASH_STAT_OK;
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}
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