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riscv-openocd/contrib/loaders/checksum/Makefile

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contrib: add GPL license tag on files that miss it Some file miss completely the license tag. Add the SPDX tag, using the same GPL-2.0-or-later license of the OpenOCD project. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I24bd362eeb6b74f09aceb9b757d45cbfa4afe334 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7160 Tested-by: jenkins
2022-08-30 17:20:16 -05:00
# SPDX-License-Identifier: GPL-2.0-or-later
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 13:41:51 -05:00
BIN2C = ../../../src/helper/bin2char.sh
ARM_CROSS_COMPILE ?= arm-none-eabi-
ARM_AS ?= $(ARM_CROSS_COMPILE)as
ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
contrib/loaders: Enforce Little Endian ARM machine code arm-none-eabi target triplet defaults to Little Endian, and so far any submitted machine code snippets have been verified to be Little Endian. However a user might override [ARM_]CROSS_COMPILE with an armeb toolchain, potentially resulting in invalid machine code. Let's be safe and enforce Little Endian mode for assembler and compiler. Change-Id: I9cefe24689eaded25d60ffb1f254b254e8d76f9d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3498 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-21 17:41:15 -05:00
ARM_AFLAGS = -EL
Implement CRC32 algorithm for RISC-V. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01 Reviewed-on: http://openocd.zylin.com/6076 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-03-03 14:41:03 -06:00
RISCV_CROSS_COMPILE ?= riscv64-unknown-elf-
RISCV_CC ?= $(RISCV_CROSS_COMPILE)gcc
RISCV_OBJCOPY ?= $(RISCV_CROSS_COMPILE)objcopy
RISCV32_CFLAGS = -march=rv32e -mabi=ilp32e -nostdlib -nostartfiles -Os -fPIC
RISCV64_CFLAGS = -march=rv64i -mabi=lp64 -nostdlib -nostartfiles -Os -fPIC
all: arm riscv
armv4_5: Integrate build of checksum code Add rules to build armv4_5_crc.inc, and convert the code to target endianness the least intrusive way. Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3473 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-08 13:12:12 -05:00
arm: armv4_5_crc.inc armv7m_crc.inc
Implement CRC32 algorithm for RISC-V. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01 Reviewed-on: http://openocd.zylin.com/6076 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-03-03 14:41:03 -06:00
riscv: riscv32_crc.inc riscv64_crc.inc
armv4_5: Integrate build of checksum code Add rules to build armv4_5_crc.inc, and convert the code to target endianness the least intrusive way. Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3473 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-08 13:12:12 -05:00
armv4_5_%.elf: armv4_5_%.s
contrib/loaders: Enforce Little Endian ARM machine code arm-none-eabi target triplet defaults to Little Endian, and so far any submitted machine code snippets have been verified to be Little Endian. However a user might override [ARM_]CROSS_COMPILE with an armeb toolchain, potentially resulting in invalid machine code. Let's be safe and enforce Little Endian mode for assembler and compiler. Change-Id: I9cefe24689eaded25d60ffb1f254b254e8d76f9d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3498 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-21 17:41:15 -05:00
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv4_5: Integrate build of checksum code Add rules to build armv4_5_crc.inc, and convert the code to target endianness the least intrusive way. Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3473 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-08 13:12:12 -05:00
armv4_5_%.bin: armv4_5_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 13:41:51 -05:00
armv7m_%.elf: armv7m_%.s
contrib/loaders: Enforce Little Endian ARM machine code arm-none-eabi target triplet defaults to Little Endian, and so far any submitted machine code snippets have been verified to be Little Endian. However a user might override [ARM_]CROSS_COMPILE with an armeb toolchain, potentially resulting in invalid machine code. Let's be safe and enforce Little Endian mode for assembler and compiler. Change-Id: I9cefe24689eaded25d60ffb1f254b254e8d76f9d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3498 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-21 17:41:15 -05:00
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 13:41:51 -05:00
armv7m_%.bin: armv7m_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
Implement CRC32 algorithm for RISC-V. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01 Reviewed-on: http://openocd.zylin.com/6076 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-03-03 14:41:03 -06:00
%.inc: %.bin
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 13:41:51 -05:00
$(BIN2C) < $< > $@
Implement CRC32 algorithm for RISC-V. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01 Reviewed-on: http://openocd.zylin.com/6076 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-03-03 14:41:03 -06:00
riscv32_%.elf: riscv_%.c
$(RISCV_CC) $(RISCV32_CFLAGS) $< -o $@
riscv64_%.elf: riscv_%.c
$(RISCV_CC) $(RISCV64_CFLAGS) $< -o $@
riscv%.bin: riscv%.elf
$(RISCV_OBJCOPY) -Obinary $< $@
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 13:41:51 -05:00
clean:
-rm -f *.elf *.bin *.inc