112 lines
3.3 KiB
INI
112 lines
3.3 KiB
INI
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# The ESP32-C2 only supports JTAG.
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transport select jtag
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# Source the ESP common configuration file
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source [find target/esp_common.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME esp32c2
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0000cc25
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}
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set _TARGETNAME $_CHIPNAME
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set _CPUNAME cpu
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set _TAPNAME $_CHIPNAME.$_CPUNAME
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jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
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proc esp32c2_wdt_disable { } {
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# Halt event can occur during config phase (before "init" is done).
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# Ignore it since mww commands don't work at that time.
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if { [string compare [command mode] config] == 0 } {
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return
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}
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# Timer Group 0 WDT
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mww 0x6001f064 0x50D83AA1
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mww 0x6001F048 0
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# RTC WDT
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mww 0x6000809C 0x50D83AA1
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mww 0x60008084 0
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# SWD
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mww 0x600080A4 0x8F1D312A
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mww 0x600080A0 0x84B00000
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}
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# This is almost identical with the esp32c3_soc_reset.
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# Will be refactored with the other common settings.
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proc esp32c2_soc_reset { } {
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# This procedure does "digital system reset", i.e. resets
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# all the peripherals except for the RTC block.
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# It is called from reset-assert-post target event callback,
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# after assert_reset procedure was called.
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# Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
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# temporarily take it out of reset. Save the dmcontrol state before
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# doing so.
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riscv dmi_write 0x10 0x80000001
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# Trigger the reset
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mww 0x60008000 0x9c00a000
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# Workaround for stuck in cpu start during calibration.
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# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
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mww 0x6001F068 0
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# Wait for the reset to happen
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sleep 10
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poll
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# Disable the watchdogs again
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esp32c2_wdt_disable
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# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
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# We will clean allhalted state by resuming the core.
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riscv dmi_write 0x10 0x40000001
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# Put the hart back into reset state. Note that we need to keep haltreq set.
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riscv dmi_write 0x10 0x80000003
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}
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if { $_RTOS == "none" } {
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target create $_TARGETNAME riscv -chain-position $_TAPNAME
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} else {
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target create $_TARGETNAME riscv -chain-position $_TAPNAME -rtos $_RTOS
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}
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$_TARGETNAME configure -event reset-assert-post { esp32c2_soc_reset }
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$_TARGETNAME configure -event halted {
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esp32c2_wdt_disable
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}
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$_TARGETNAME configure -event examine-end {
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# Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
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arm semihosting enable
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arm semihosting_resexit enable
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if { [info exists _SEMIHOST_BASEDIR] } {
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if { $_SEMIHOST_BASEDIR != "" } {
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# TODO: cherry-pick from upstream
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# https://review.openocd.org/c/openocd/+/6888
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# https://review.openocd.org/c/openocd/+/7005
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# arm semihosting_basedir $_SEMIHOST_BASEDIR
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}
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}
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}
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$_TARGETNAME configure -event gdb-attach {
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halt 1000
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# by default mask interrupts while stepping
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riscv set_maskisr steponly
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}
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gdb_breakpoint_override hard
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riscv set_reset_timeout_sec 2
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riscv set_command_timeout_sec 5
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riscv set_mem_access sysbus progbuf abstract
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riscv set_ebreakm on
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riscv set_ebreaks on
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riscv set_ebreaku on
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