2008-02-28 04:07:54 -06:00
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#Script for AT91EB40a
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2008-11-30 16:25:43 -06:00
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91eb40a
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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2008-12-01 07:20:59 -06:00
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set _CPUTAPID 0x1f0f0f0f
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2008-11-30 16:25:43 -06:00
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}
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2008-02-28 04:07:54 -06:00
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#Atmel ties SRST & TRST together, at which point it makes
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#no sense to use TRST, but use TMS instead.
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#
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#The annoying thing with tying SRST & TRST together is that
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#there is no way to halt the CPU *before and during* the
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#SRST reset, which means that the CPU will run a number
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#of cycles before it can be halted(as much as milliseconds).
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reset_config srst_only srst_pulls_trst
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#jtag scan chain
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#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
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2008-11-30 16:25:43 -06:00
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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2008-02-28 04:07:54 -06:00
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#target configuration
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2009-09-04 00:17:03 -05:00
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set _TARGETNAME $_CHIPNAME.cpu
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2008-11-30 16:25:43 -06:00
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
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2008-02-28 04:07:54 -06:00
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# speed up memory downloads
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2008-07-11 07:17:56 -05:00
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arm7_9 fast_memory_access enable
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2008-02-28 04:07:54 -06:00
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arm7_9 dcc_downloads enable
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2008-04-04 08:47:38 -05:00
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#flash driver
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flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
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2008-02-28 04:07:54 -06:00
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# required for usable performance. Used for lots of
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# other things than flash programming.
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2008-11-30 16:25:43 -06:00
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
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2008-08-15 09:59:03 -05:00
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2008-11-30 16:25:43 -06:00
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$_TARGETNAME configure -event reset-init {
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2008-08-11 07:28:38 -05:00
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puts "Running reset init script for AT91EB40A"
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2008-07-11 04:06:36 -05:00
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# Reset script for AT91EB40a
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reg cpsr 0x000000D3
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mww 0xFFE00020 0x1
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mww 0xFFE00024 0x00000000
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mww 0xFFE00000 0x01002539
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mww 0xFFFFF124 0xFFFFFFFF
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mww 0xffff0010 0x100
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mww 0xffff0034 0x100
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}
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