2009-10-26 12:06:05 -05:00
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# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
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# The board has separate JTAG ports for cpu and CPLD/FPGA devices
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# Chaining is done on IO interfaces if desired.
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source [find target/pxa270.cfg]
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# The board supports separate reset lines
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# Override this in the interface config for parallel dongles
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reset_config trst_and_srst separate
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# flash bank <driver> <base> <size> <chip_width> <bus_width>
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# 29LV650 64Mbit Flash
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2009-11-18 04:15:52 -06:00
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 0
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