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riscv-openocd/tcl/target/stm32mp15x.cfg

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tcl/target: add SPDX tag For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl/ target| while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7027 Tested-by: jenkins
2022-06-12 16:42:27 -05:00
# SPDX-License-Identifier: GPL-2.0-or-later
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
# http://www.st.com/stm32mp1
# HLA does not support multi-cores nor custom CSW nor AP other than 0
if { [using_hla] } {
echo "ERROR: HLA transport cannot work with this target."
echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
shutdown
}
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32mp15x
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
set _CPUTAPID 0x6ba00477
} else {
set _CPUTAPID 0x6ba02477
}
}
# Chip Level TAP Controller, only in jtag mode
if { [info exists CLCTAPID] } {
set _CLCTAPID $CLCTAPID
} else {
set _CLCTAPID 0x06500041
}
swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
if { [using_jtag] } {
jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
# so defer-examine it until the reset framework get merged
# NOTE: keep ap-num and dbgbase to speed-up examine after reset
# NOTE: do not change the order of target create
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
targets $_CHIPNAME.cpu0
target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
$_CHIPNAME.cpu0 cortex_a maskisr on
$_CHIPNAME.cpu1 cortex_a maskisr on
$_CHIPNAME.cpu0 cortex_a dacrfixup on
$_CHIPNAME.cpu1 cortex_a dacrfixup on
tcl: replace '-ctibase' with '-baseaddr' Replace the deprecated option '-ctibase' with the generic option '-baseaddr'. Change generated with command: sed -i 's/-ctibase/-baseaddr/g' $(find tcl/ -type f) Change-Id: If776934d2ac106532708768bb3a4ec6fcffb0368 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5870 Tested-by: jenkins
2020-10-17 12:25:50 -05:00
cti create $_CHIPNAME.cti.sys -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
cti create $_CHIPNAME.cti.cm4 -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
tcl/target: start using the new TPIU/SWO support Create the TPIU and SWO device in target config file. Replace the target event 'trace-config' with the TPIU/SWO event 'post-enable'. Extend the existing code in the event handler to properly set the gpio mode and speed to permit synchronous trace. This patch is not exhaustive of all the targets that have SWO, but has to be considered as an initial example. Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5859 Tested-by: jenkins Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2020-10-11 17:12:05 -05:00
swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
# interface does not work while srst is asserted
# this is target specific, valid for every board
# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
# debug unit, behavior equivalent to "srst_pulls_trst"
reset_config srst_gates_jtag srst_pulls_trst
adapter speed 5000
adapter srst pulse_width 200
# bootrom has an internal timeout of 1 second for detecting the boot flash.
# wait at least 1 second to guarantee we are out of bootrom
adapter srst delay 1100
add_help_text axi_secure "Set secure mode for following AXI accesses"
proc axi_secure {} {
$::_CHIPNAME.dap apsel 0
$::_CHIPNAME.dap apcsw 0x10006000
}
add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
proc axi_nsecure {} {
$::_CHIPNAME.dap apsel 0
$::_CHIPNAME.dap apcsw 0x30006000
}
axi_secure
proc dbgmcu_enable_debug {} {
# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
tcl/stm32mp15x: freeze watchdog, recover SWD after power cycle Freeze the IWDG watchdog when cores are halted to prevent a reset while debugging. The PMIC present on some board senses the nsrst and forces a power cycle to the target. The power cycle causes the SWJ-DP to restart in JTAG mode. If the debugger is using SWD, the mismatch triggers an error after the reset command. Ignore the error detected by 'dap init' and proceed executing the handler. The error in 'dap init' will force a reconnect during the following 'dap apid', restoring the SWD functionality. Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6599 Tested-by: jenkins
2021-04-07 12:21:27 -05:00
# freeze watchdog 1 and 2 on cores halted
catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
}
proc toggle_cpu0_dbg_claim0 {} {
# toggle CPU0 DBG_CLAIM[0]
$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
}
proc detect_cpu1 {} {
Remove all occurrences of 'mem2array' and 'array2mem' Replace deprecated commands 'mem2array' and 'array2mem' with new Tcl commands 'read_memory' and 'write_memory'. Change-Id: I116d995995396133ca782b14cce02bd1ab917a4e Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/6859 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-25 08:44:58 -06:00
set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
set dual_core [expr {$cpu1_prsr & 1}]
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}
tcl/target: start using the new TPIU/SWO support Create the TPIU and SWO device in target config file. Replace the target event 'trace-config' with the TPIU/SWO event 'post-enable'. Extend the existing code in the event handler to properly set the gpio mode and speed to permit synchronous trace. This patch is not exhaustive of all the targets that have SWO, but has to be considered as an initial example. Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5859 Tested-by: jenkins Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2020-10-11 17:12:05 -05:00
proc rcc_enable_traceclk {} {
$::_CHIPNAME.ap2 mww 0x5000080c 0x301
}
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
# FIXME: most of handler below will be removed once reset framework get merged
tcl/stm32mp15x: freeze watchdog, recover SWD after power cycle Freeze the IWDG watchdog when cores are halted to prevent a reset while debugging. The PMIC present on some board senses the nsrst and forces a power cycle to the target. The power cycle causes the SWJ-DP to restart in JTAG mode. If the debugger is using SWD, the mismatch triggers an error after the reset command. Ignore the error detected by 'dap init' and proceed executing the handler. The error in 'dap init' will force a reconnect during the following 'dap apid', restoring the SWD functionality. Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6599 Tested-by: jenkins
2021-04-07 12:21:27 -05:00
$_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
tcl/target: start using the new TPIU/SWO support Create the TPIU and SWO device in target config file. Replace the target event 'trace-config' with the TPIU/SWO event 'post-enable'. Extend the existing code in the event handler to properly set the gpio mode and speed to permit synchronous trace. This patch is not exhaustive of all the targets that have SWO, but has to be considered as an initial example. Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5859 Tested-by: jenkins Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2020-10-11 17:12:05 -05:00
$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug;rcc_enable_traceclk}
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
$_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine}
$_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer}
$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
tcl: stm32mp15x: fix "reset halt" on CM4 in engineering boot The state machine of cortex-m have to pass through a set of state before it get in "halted". Add one more "arp_poll" to achieve the proper state during a "reset halt" command in engineering boot. Change-Id: I90828bf20ef75bd4018f8b911f727ae69c4d6e8f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5649 Tested-by: jenkins Reviewed-by: Richard Braun <rbraun@sceen.net>
2020-05-05 11:11:47 -05:00
$_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
tcl: stm32mp15x: add target and board config files The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and one Cortex-M4. The second core is automatically detected by the target script. In "engineering boot" all the cores are accessible. In "production boot" the Cortex-M4 is kept in reset state after power-on or NRST. The board DK2 includes a ST-Link/V2, but only SWD is connected. Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5454 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-14 09:49:45 -06:00
$_CHIPNAME.ap1 configure -event examine-start {dap init}
$_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug}
$_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1}
tcl/target: start using the new TPIU/SWO support Create the TPIU and SWO device in target config file. Replace the target event 'trace-config' with the TPIU/SWO event 'post-enable'. Extend the existing code in the event handler to properly set the gpio mode and speed to permit synchronous trace. This patch is not exhaustive of all the targets that have SWO, but has to be considered as an initial example. Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5859 Tested-by: jenkins Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2020-10-11 17:12:05 -05:00
$_CHIPNAME.ap2 configure -event examine-end {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}