2013-01-10 02:31:45 -06:00
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/***************************************************************************
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* Copyright (C) 2011 by Andreas Fritiofson *
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* andreas.fritiofson@gmail.com *
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* Copyright (C) 2013 by Roman Dmitrienko *
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* me@iamroman.org *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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2013-06-02 14:32:36 -05:00
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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2013-01-10 02:31:45 -06:00
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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/* Params:
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* r0 - flash base (in), status (out)
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* r1 - count (word-32bit)
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* r2 - workarea start
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* r3 - workarea end
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* r4 - target address
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* Clobbered:
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* r5 - rp
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* r6 - wp, tmp
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* r7 - tmp
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*/
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/* offsets of registers from flash reg base */
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#define EFM32_MSC_WRITECTRL_OFFSET 0x008
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#define EFM32_MSC_WRITECMD_OFFSET 0x00c
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#define EFM32_MSC_ADDRB_OFFSET 0x010
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#define EFM32_MSC_WDATA_OFFSET 0x018
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#define EFM32_MSC_STATUS_OFFSET 0x01c
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/* set WREN to 1 */
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movs r6, #1
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str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
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wait_fifo:
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ldr r6, [r2, #0] /* read wp */
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cmp r6, #0 /* abort if wp == 0 */
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beq exit
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ldr r5, [r2, #4] /* read rp */
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cmp r5, r6 /* wait until rp != wp */
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beq wait_fifo
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/* store address in MSC_ADDRB */
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str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
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/* set LADDRIM bit */
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movs r6, #1
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str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
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/* check status for INVADDR and/or LOCKED */
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ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
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movs r7, #6
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tst r6, r7
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bne error
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/* wait for WDATAREADY */
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wait_wdataready:
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ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
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movs r7, #8
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tst r6, r7
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beq wait_wdataready
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/* load data to WDATA */
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ldr r6, [r5]
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str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
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/* set WRITEONCE bit */
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movs r6, #8
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str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
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adds r5, #4 /* rp++ */
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adds r4, #4 /* target_address++ */
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/* wait until BUSY flag is reset */
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busy:
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ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
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movs r7, #1
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tst r6, r7
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bne busy
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cmp r5, r3 /* wrap rp at end of buffer */
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bcc no_wrap
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mov r5, r2
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adds r5, #8
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no_wrap:
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str r5, [r2, #4] /* store rp */
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subs r1, r1, #1 /* decrement word count */
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cmp r1, #0
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beq exit /* loop if not done */
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b wait_fifo
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error:
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movs r0, #0
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str r0, [r2, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0
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