riscv-openocd/tcl/target/stm32h7x_dual_bank.cfg

# script for stm32h7x family (dual flash bank)

# STM32H7xxxI 2Mo have a dual bank flash.
set DUAL_BANK 1

source [find target/stm32h7x.cfg]
Add STM32H7 config files Add 2 target files: -stm32h7x.cfg -stm32h7x_dual_bank.cfg Add 2 config files for: -STM32H743zi-nucleo bord -STM32H743i and STM32H753i eval boards. Change-Id: I2aae2c5acff4f3ff8e1bf232fda5a11a87f71703 Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-on: http://openocd.zylin.com/4182 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> 2017-11-13 10:00:58 -06:00			`# script for stm32h7x family (dual flash bank)`

			`# STM32H7xxxI 2Mo have a dual bank flash.`
target/stm32h7x: add support of dual core variant of STM32H7 STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4 The second core creation is only done when * DUAL_CORE variable is set to true * non HLA interface is used A second check for the second core existence is done in cpu1 examine-end Once the second core is detected it gets examined. Furthermore, the script provides a configurable CTI usage in order to halt the cores simultaneously. Tested on Rev X and V devices. PS: the indentation was a mix of spaces and tabs, all changed to tabs. Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5130 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> 2019-11-27 12:10:34 -06:00			`set DUAL_BANK 1`

			`source [find target/stm32h7x.cfg]`